SoC Synthesis Engineer: RTL-to-Gate & PPA Optimizer

Qualcomm; Tijuana; Presencial; MXN 1.223.989 - 1.661.129; Jornada completa

Descripción de la vacante

Qualcomm is seeking a SoC Design & Synthesis Engineer in Tijuana, Baja California. This role is essential for synthesizing large-scale SoC RTL designs into high-quality gate-level netlists, ensuring design efficiency across multiple platforms such as mobile and automotive.

Ideal candidates should have robust experience in ASIC design, with an emphasis on RTL-to-gate synthesis, timing constraints, and optimization techniques. The job offers a dynamic environment where you'll collaborate with various teams to deliver high-performance products.

Formación

• 2+ years of ASIC design or related experience with a Bachelor's degree.
• 1+ year experience with a Master's degree in related field.
• PhD in Science, Engineering, or related field.

Responsabilidades

• Synthesize large-scale SoC RTL designs into gate-level netlists.
• Optimize PPA by analyzing trade-offs.
• Support functional ECOs and validate designs.

Conocimientos

RTL-to-gate synthesis

Gate-level netlist quality checks

Timing constraints knowledge

PPA optimization

Functional ECOs experience

Analytical thinking

Educación

Bachelor's degree in Science, Engineering or related field

Master’s or PhD in related field

Herramientas

EDA tools

Architecture/design tools

Scripting tools

Descripción del empleo

Qualcomm is seeking a SoC Design & Synthesis Engineer in Tijuana, Baja California. This role is essential for synthesizing large-scale SoC RTL designs into high-quality gate-level netlists, ensuring design efficiency across multiple platforms such as mobile and automotive.

Ideal candidates should have robust experience in ASIC design, with an emphasis on RTL-to-gate synthesis, timing constraints, and optimization techniques. The job offers a dynamic environment where you'll collaborate with various teams to deliver high-performance products.