Senior SoC Verification Engineer — UVM, Coverage & Debug

Semiconductor Engineering; Región Centro; Presencial; MXN 420.000 - 640.000; Jornada completa

Descripción de la vacante

Semiconductor Engineering is seeking a hands-on SoC Design Verification Engineer to drive verification for complex SoC/IP blocks. You will own verification planning, UVM testbench development, test content creation (directed and constrained-random), coverage closure, and debug across block, subsystem, and SoC levels.

You will collaborate with design, architecture, firmware, and validation teams to deliver high-quality silicon on schedule, ensuring robust verification strategies and timely

Formación

• Experience planning verification for complex SoC/IP blocks.
• UVM testbench development experience.
• Coverage closure and debug across block, subsystem, and SoC.

Responsabilidades

• Own verification planning and execution.
• Develop UVM testbenches and test content.
• Create directed and constrained-random tests.
• Drive coverage closure and debug across levels.

Conocimientos

SoC verification

UVM

Directed testing

Constrained-random testing

Descripción del empleo

Semiconductor Engineering is seeking a hands-on SoC Design Verification Engineer to drive verification for complex SoC/IP blocks. You will own verification planning, UVM testbench development, test content creation (directed and constrained-random), coverage closure, and debug across block, subsystem, and SoC levels.

You will collaborate with design, architecture, firmware, and validation teams to deliver high-quality silicon on schedule, ensuring robust verification strategies and timely