SoC Verification Engineer: UVM Testbenches, Coverage Lead

Semiconductor Engineering; Costa Rica; Presencial; MXN 1.544.000 - 2.230.000; Jornada completa

Descripción de la vacante

Semiconductor Engineering seeks a hands-on SoC Design Verification Engineer to drive verification for complex SoC/IP blocks. You will own verification planning, UVM testbench development, directed and constrained-random test content, coverage closure, and debug across block, subsystem, and SoC levels.

You’ll collaborate with design, architecture, firmware, and validation teams to deliver high-quality silicon on schedule.

Descripción del empleo

Semiconductor Engineering seeks a hands-on SoC Design Verification Engineer to drive verification for complex SoC/IP blocks. You will own verification planning, UVM testbench development, directed and constrained-random test content, coverage closure, and debug across block, subsystem, and SoC levels.

You’ll collaborate with design, architecture, firmware, and validation teams to deliver high-quality silicon on schedule.