Senior Principal Memory Layout Architect

Micron Technology, Inc; Tlaquepaque; Presencial; MXN 1.040.402 - 1.560.603; Jornada completa

Ventajas ofrecidas por este puesto de trabajo

Medical, dental, and vision plans

Income protection programs

Paid family leave

Paid time-off program

Paid holidays

Descripción de la vacante

Micron Technology, Inc in Tlaquepaque, Jalisco, is seeking a Lead Principal Engineer in Layout Design to lead the layout build and physical realization of innovative memory products. This role is critical in turning specifications into manufacturable layouts through collaboration with a world-class team.

The ideal candidate should have over 10 years of semiconductor experience and a Bachelor's degree in Electrical Engineering. This position involves optimizing layout techniques and maintaining documentation, offering a comprehensive benefits package.

Formación

• 10+ years of experience in the Semiconductor industry.
• Strong understanding of CMOS devices and layout-dependent effects.
• Experience leading technical execution and delivering tapeouts.

Responsabilidades

• Lead the layout build and physical realization of new memory products.
• Produce layout collateral and documentation for cross-team integration.
• Run and debug physical verification flows and ensure closure.

Conocimientos

CMOS devices knowledge

Custom IC layout experience

Physical verification tools

Scripting/automation proficiency

Problem-solving skills

Educación

Bachelor's degree in Electrical Engineering

Master's Degree or PhD in Electrical/Computer Engineering

Herramientas

EDA tools

Descripción del empleo

Micron Technology, Inc in Tlaquepaque, Jalisco, is seeking a Lead Principal Engineer in Layout Design to lead the layout build and physical realization of innovative memory products. This role is critical in turning specifications into manufacturable layouts through collaboration with a world-class team.

The ideal candidate should have over 10 years of semiconductor experience and a Bachelor's degree in Electrical Engineering. This position involves optimizing layout techniques and maintaining documentation, offering a comprehensive benefits package.