Senior Analog Layout Architect for High-Performance Memory

3050 Micron Semiconductor Mexico, S.de R.L. de C.V.

Región Centro

Presencial

MXN 600.000 - 850.000

Jornada completa

Hace 9 días

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Descripción de la vacante

Micron Technology in Guadalajara, Mexico is seeking a Layout Design Engineer to work on analog, mixed-signal and full-chip layouts for advanced CMOS processes. You will contribute to high-performance memory designs and collaborate with global teams across multiple projects.

The role requires 5+ years in analog/layout, a BE or MTech in Electronic/VLSI, and proficiency with Cadence VLE/VXL and Calibre DRC/LVS.

Formación

  • 5+ years of analog/custom layout design in advanced CMOS process.
  • BE or MTech in Electronic/VLSI Engineering.
  • Expertise in Cadence VLE/VXL and Mentor Calibre DRC/LVS.
  • Hands-on experience in creating layouts for critical blocks (PLL, ADC, DAC, LDO, etc.).
  • Knowledge of analog layout fundamentals and layout effects on speed, power, area.
  • Ability to plan, estimate and manage multiple layout projects.

Responsabilidades

  • Design and development of analog, mixed-signal, custom digital block and full chip layouts.
  • Perform LVS/DRC/Antenna checks and documentation.
  • Ensure on-time delivery of block-level layouts with high quality.
  • Lead planning, area/time estimation, scheduling and delegation across projects.
  • Communicate effectively with global engineering teams to ensure project success.

Conocimientos

Analog layout
Planar/FinFET
LVS/DRC
Block-level layouts
Temperature sensor/PLL/ADC/DAC
Layout constraints & optimization

Educación

BE or MTech in Electronic/VLSI

Herramientas

Cadence VLE/VXL
Mentor Calibre DRC/LVS

Descripción del empleo

Micron Technology in Guadalajara, Mexico is seeking a Layout Design Engineer to work on analog, mixed-signal and full-chip layouts for advanced CMOS processes. You will contribute to high-performance memory designs and collaborate with global teams across multiple projects.

The role requires 5+ years in analog/layout, a BE or MTech in Electronic/VLSI, and proficiency with Cadence VLE/VXL and Calibre DRC/LVS.

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