Senior High-Speed Package & PCB Layout Engineer

Semtech

Aguascalientes

Vor Ort

MXN 1.413.000 - 1.642.000

Vollzeit

Vor 8 Tagen

Eine vollständige Bewerbung in einer Minute

Maßgeschneiderter Lebenslauf und Anschreiben – versandbereit.

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Zusammenfassung

Semtech Corporation is seeking a motivated Package and PCB Layout Engineer to join our R&D hardware design team. You will contribute to high‑speed designs across interconnect technologies and be a key member of the Signal Integrity Products unit.

The role focuses on package feasibility studies, multi‑layer substrate layouts, and wafer‑level interconnect layouts, collaborating with manufacturing, thermo‑mechanical engineering, and international suppliers in a fast‑paced environment.

Qualifikationen

  • Bachelor’s degree in engineering, physics, or a related field.
  • Minimum 5 years of layout experience in high-speed package or advanced PCB technologies.
  • Solid knowledge of high-speed layout and electronic design.
  • Advanced knowledge of EDA layout tools.
  • Familiarity with PCB layout and mechanical, thermal, and optical design.
  • Understanding of RF, analog, and digital circuits.
  • Ability to coordinate with cross-functional teams and suppliers.

Aufgaben

  • Perform package design feasibility assessments with SI/manufacturing teams.
  • Develop multi-layer substrate and carrier layouts for 2D/2.5D/3D IC configurations.
  • Create wafer-level interconnect layouts using redistribution layers and wafer reconstruction.

Kenntnisse

High-speed layout
Electronic design
Cross-functional collaboration
Communication
Parallel work with teams

Ausbildung

Bachelor's degree in engineering or physics

Tools

Cadence APD
Cadence Allegro

Jobbeschreibung

Semtech Corporation is seeking a motivated Package and PCB Layout Engineer to join our R&D hardware design team. You will contribute to high‑speed designs across interconnect technologies and be a key member of the Signal Integrity Products unit.

The role focuses on package feasibility studies, multi‑layer substrate layouts, and wafer‑level interconnect layouts, collaborating with manufacturing, thermo‑mechanical engineering, and international suppliers in a fast‑paced environment.

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