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Ciena is seeking an Analog Layout Engineer in Mexico to contribute to high-speed optical circuit layouts using deep-submicron CMOS and BiCMOS processes. You will design analog blocks, perform DRC/LVS checks, and collaborate with senior designers to optimize trade-offs for performance and yield.
The ideal candidate has a Bachelor's in Electrical Engineering, 5+ years in analog/mixed-signal layout, and proficiency with Cadence Virtuoso, Calibre, and Totem.
Ciena is seeking an Analog Layout Engineer in Mexico to contribute to high-speed optical circuit layouts using deep-submicron CMOS and BiCMOS processes. You will design analog blocks, perform DRC/LVS checks, and collaborate with senior designers to optimize trade-offs for performance and yield.
The ideal candidate has a Bachelor's in Electrical Engineering, 5+ years in analog/mixed-signal layout, and proficiency with Cadence Virtuoso, Calibre, and Totem.