NCG DRAM Design Technology Layout Engineer

Micron Technology, Inc.; Tlaquepaque; On-site; MXN 700,000 - 1,000,000; Full time

Benefits offered by this job

Medical, dental and vision plans

Paid time off

Paid holidays

Job summary

Micron Technology, Inc. in Mexico seeks a Layout Engineer for DRAM design to translate schematics into physical layouts used to generate fabrication reticles.

You will apply digital and analog layout techniques while partnering with design, CAD, and engineering teams to meet product, process, quality, and schedule requirements. You will build expertise in advanced semiconductor processes, verification, mask generation, and tapeout while helping us innovate and improve layout methodologies.

Qualifications

• Bachelor's degree or equivalent in a technical field with EE foundation.
• Experience developing IP layouts using CMOS processes and physical verification.
• Proficiency in layout rules, routing, and reliability considerations.
• Ability to interpret schematics and evaluate layout impacts on performance and area.
• Experience with layout tools (Cadence Virtuoso) and physical verification (Calibre).

Responsibilities

• Develop and optimize IP layouts for DRAM products using digital/analog techniques.
• Perform LVS/DRC, EM analysis, and other verification tasks with quality checks.
• Plan layout activities, estimate effort, and ensure timely delivery.
• Collaborate with circuit designers, CAD teams, and global partners to resolve issues.
• Develop and improve layout methodologies and automation to boost efficiency.

Skills

CMOS layouts

Layout fundamentals

Electromigration

Device matching

Parasitic analysis

Crosstalk

IR drop

LVS/DRC

Education

Electrical/ Electronics/ related engineering degree

Tools

Cadence Virtuoso

Siemens Calibre

Job description

Req ID:

JR101718 NCG DRAM Design Technology Layout Engineer

Our vision is to transform how the world uses information to enrich life for all.

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

As part of our DRAM Design Engineering Group, you will develop and craft physical layouts that translate circuit schematics into designs used to create fabrication reticles for advanced DRAM products. You will apply digital and analog layout techniques while collaborating with design, CAD, and engineering teams to meet product, process, quality, and schedule requirements.

In this role, you will build expertise in advanced semiconductor processes, verification, mask generation, and tapeout while helping us innovate and improve layout methodologies. Your work will have a direct impact on design quality, reliability, performance, and engineering efficiency as we develop next-generation memory solutions!

Responsibilities:

• Develop and optimize intellectual property (IP) layouts for DRAM products, applying digital and analog layout techniques to meet design, area, performance, and process requirements.


• Perform physical design verification, including Layout Versus Schematic (LVS), Design Rule Checking (DRC), electromigration (EM) analysis, quality checks, and technical documentation.


• Drive timely delivery of high-quality block-level layouts by planning layout activities, estimating area and effort, prioritizing work, and identifying solutions to technical challenges.


• Collaborate with circuit designers, CAD teams, and global engineering partners to review layouts, resolve issues, and support successful project execution.


• Develop and improve layout methodologies, automation approaches, and problem-solving practices that enhance design quality and engineering efficiency.

Minimum Qualifications:

• Bachelor’s degree or equivalent experience in Electrical Engineering, Electronics Engineering, Mechatronics, Robotics, Biomedical Engineering, or a related technical field with an electrical engineering foundation.


• Experience developing IP layouts using advanced Complementary Metal‑Oxide‑Semiconductor (CMOS) processes, including physical verification of complex designs against provided specifications.


• Proficiency in layout fundamentals and optimization techniques, including design rules, routing, device matching, electromigration, latch‑up, coupling, crosstalk, IR drop, parasitic analysis, shielding, yield, and reliability.


• Experience interpreting schematics and evaluating layout effects on circuit speed, capacitance, power, performance, and area, with strong analytical and problem‑solving skills.


• Experience with Cadence Virtuoso or comparable layout tools and physical verification tools such as Siemens Calibre, along with the interpersonal skills to collaborate effectively with circuit designers, CAD teams, and other engineering partners.

Preferred Qualifications:

• Experience with SKILL programming, layout automation, or related approaches that improve engineering efficiency.


• Demonstrated ability to learn, prioritize work, and contribute effectively across multiple projects in a collaborative engineering environment.


• Leadership experience through technical planning, project execution, mentoring, or collaboration with fellow team members.


• Strong written and verbal communication skills for working with globally distributed engineering teams.


• Interest or experience using AI, generative AI, or AI‑enabled engineering tools to innovate, support technical problem‑solving, and improve productivity.

Layout/Mask Designer E1

Relocation Level: TBD

"The specified role does not encompass the following responsibilities: Finalization of sales agreements or the execution of sales contracts is prohibited. The role also does not carry the authority to make definitive decisions regarding contracts, be it their conclusion or termination. Furthermore, the role is not designed to involve participation in pricing negotiations or the authorization of contracts. These activities fall beyond the permissible duties of the position."

As a world leader in the semiconductor industry, Micron is dedicated to your personal wellbeing and professional growth. Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future. We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget. Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave. Additionally, Micron benefits include a robust paid time‑off program and paid holidays. For additional information regarding the Benefit programs available, please see the Benefits Guide posted on Benefits | Micron Technology, Inc

Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.