Senior Package Layout Engineer — 2.5D/3D-IC Packaging Lead

Amazon Inc.; Asti; Ibrido; EUR 163.000 - 253.000; Tempo pieno

Vantaggi offerti da questo lavoro

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RSUs

Health insurance

401(k) matching

Paid time off

Descrizione del lavoro

Annapurna Labs, an Amazon AWS organization, is seeking a Sr. Package Layout Engineer to lead end-to-end physical design of advanced IC packages for AI silicon and data center ASICs.

You will own layout from floor planning through tape-out, collaborating with silicon, SI/PI, thermal, and manufacturing teams to meet performance and reliability targets. Responsibilities include driving 2.5D/3D packaging architectures, RDL/substrate routing, cross‑level optimization, and coordination with OSAT

Competenze

• Bachelor's degree in Electrical Engineering or related field.
• 10+ years of IC package layout and physical design experience.
• Proven track record leading package designs from concept to tape out for complex substrates or interposers.
• Hands-on with Cadence APD/SiP, Synopsys IC Packaging, Mentor Xpedition or equivalent.
• Deep understanding of 2.5D/3D-IC, fan-out WLP, RDL, TSV, microbumps, and silicon bridge interconnects.

Mansioni

• Lead full package layout cycle from floor planning to tape out release.
• Drive physical design of 2.5D/3D packaging architectures and related interposers.
• Define and optimize floorplans, power/ground, and high-speed routing.
• Perform RDL and substrate routing for high-density interconnects.
• Coordinate die‑package interface optimization with ASIC teams.
• Ensure DFM compliance and drive design closure with zero escapes.

Conoscenze

IC package layout

2.5D/3D-IC

RDL routing

Bump map definition

DFM constraints

Physical verification

OSAT coordination

Automation scripting

Formazione

Bachelor's degree in Electrical Engineering

Master's degree (preferred)

Strumenti

Cadence APD/SiP

Synopsys IC Packaging

Mentor Xpedition

Descrizione del lavoro

Annapurna Labs, an Amazon AWS organization, is seeking a Sr. Package Layout Engineer to lead end-to-end physical design of advanced IC packages for AI silicon and data center ASICs.

You will own layout from floor planning through tape-out, collaborating with silicon, SI/PI, thermal, and manufacturing teams to meet performance and reliability targets. Responsibilities include driving 2.5D/3D packaging architectures, RDL/substrate routing, cross‑level optimization, and coordination with OSAT