Senior HF RF/Analog Layout Architect - Parasitic-aware

ams OSRAM

Lombardia

In loco

EUR 90.000 - 150.000

Tempo pieno

4 giorni fa
Candidati tra i primi
Generatore di candidature

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Descrizione del lavoro

ams OSRAM is seeking a technical leader to drive HF analog layout strategy for broadband optical communication ICs or similar RF ICs. You will lead layout architecture and floorplanning, enforce methodologies, and push parasitic-aware implementations across design teams.

The role requires a BSc or MSc in Electrical Engineering and 10+ years of RF/analog layout experience, including high-speed receiver/transmitter interfaces, matching, shielding, and isolation, with advanced CMOS nodes such as

Competenze

  • BSc or MSc in Electrical Engineering.
  • 10+ years RF/analog layout experience.
  • HF analog layout for broadband optical communication ICs or comparable RF ICs, including high-speed receiver/transmitter interfaces.
  • Matching, shielding and isolation.
  • Advanced CMOS node experience, including FinFET and/or FD-SOI, is required.
  • EM-aware layout methodologies.

Mansioni

  • Technical leader responsible for HF analog layout strategy for broadband optical communication ICs or comparable RF ICs.
  • Lead layout architecture and floorplanning activities.
  • Develop and enforce layout methodologies.
  • Drive parasitic-aware implementations.
  • Support design teams through sign-off.
  • Mentor layout engineers.

Conoscenze

RF/analog layout
Parasitic-aware design
Mentorship
High-speed interfaces

Formazione

BSc/MSc in Electrical Engineering

Strumenti

FinFET/FD-SOI

Descrizione del lavoro

ams OSRAM is seeking a technical leader to drive HF analog layout strategy for broadband optical communication ICs or similar RF ICs. You will lead layout architecture and floorplanning, enforce methodologies, and push parasitic-aware implementations across design teams.

The role requires a BSc or MSc in Electrical Engineering and 10+ years of RF/analog layout experience, including high-speed receiver/transmitter interfaces, matching, shielding, and isolation, with advanced CMOS nodes such as

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