Senior CMOS Analog/Mixed-Signal Designer — NVM Memory IP

Ferroelectric Memory Company; Agrate Brianza; On-site; EUR 70,000 - 110,000; Full time

Job summary

Ferroelectric Memory GmbH (FMC) seeks an experienced IC Design Engineer with strong CMOS analog/mixed-signal design expertise and a focus on emerging NVM devices based on hafnium oxide technology. You will collaborate with international teams in Milan or Dresden to translate memory concepts into robust silicon.

Applicants should have hands-on Cadence/Verilog experience, proficiency in C and Verilog, and a solid background in analog/mixed-signal CMOS design.

Qualifications

• Experience in CMOS analog/mixed-signal IC design.
• Experience with NVM device design using hafnium oxide technology is a plus.
• Proficiency with Cadence/Verilog; programming in C and Verilog is expected.

Responsibilities

• Design and develop emerging NVM memory devices based on hafnium oxide technology.
• Define specifications and integrate analog and mixed-signal blocks into memory architecture.
• Design analog circuits for NVM memories (sense amps, decoders, bandgaps, HV regulators, ADCs).
• Run PVT simulations and circuit verification, including parasitic extraction.
• Collaborate with layout engineers to optimize robustness, matching, and area.
• Contribute to post-silicon verification and test-chip optimization.

Skills

CMOS analog/mixed-signal

NVM device design

Cadence

Verilog

C programming

Digital design concepts

Education

Degree in Electrical Engineering

Tools

Cadence design tools

Virtuoso

Spice

Verilog-A

Job description

Ferroelectric Memory GmbH (FMC) seeks an experienced IC Design Engineer with strong CMOS analog/mixed-signal design expertise and a focus on emerging NVM devices based on hafnium oxide technology. You will collaborate with international teams in Milan or Dresden to translate memory concepts into robust silicon.

Applicants should have hands-on Cadence/Verilog experience, proficiency in C and Verilog, and a solid background in analog/mixed-signal CMOS design.