Senior CMOS Analog/Mixed-Signal NVM Design Engineer

HighTech Startbahn GmbH (HTSB); Lombardia; Hybrid; EUR 60,000 - 90,000; Full time

Job summary

Ferroelectric Memory GmbH (FMC) in Dresden Germany is seeking an experienced IC Design Engineer (m/f/d) with strong CMOS analog/mixed-signal expertise and a focus on emerging NVM devices based on hafnium oxide technology. You will collaborate with international teams in Milan and Dresden to translate memory concepts into robust silicon.

The ideal candidate has 5–10 years in CMOS IC design (Analog/Mixed Signal), hands-on Cadence/Virtuoso, Verilog for modeling, and a solid understanding of memory

Qualifications

• Experience in CMOS analog/mixed-signal design and NVM device concepts.
• Proficient with Cadence tools and Verilog for modeling/verification.
• Strong cross‑functional collaboration and English proficiency.

Responsibilities

• Design and develop emerging NVM memory devices based on hafnium oxide for FMC’s ferroelectric memory product portfolio.
• Define specifications and support integration of analog and mixed-signal blocks into memory architecture.
• Design analog circuits for NVM memories (sense amps, decoders, bandgaps, HV regulators, ADCs, etc.).
• Run PVT simulations and circuit verification, including parasitic extraction.
• Collaborate with layout engineers to optimize robustness, matching, and area.
• Contribute to post‑silicon verification, debug, and optimization of memory IP and test chips.

Skills

CMOS IC design

Analog/Mixed-Signal

NVM device design

Cadence

Verilog

C programming

Digital design concepts

Education

Degree in Electrical Engineering

Tools

Cadence DFII

Virtuoso

Spice

Job description

Ferroelectric Memory GmbH (FMC) in Dresden Germany is seeking an experienced IC Design Engineer (m/f/d) with strong CMOS analog/mixed-signal expertise and a focus on emerging NVM devices based on hafnium oxide technology. You will collaborate with international teams in Milan and Dresden to translate memory concepts into robust silicon.

The ideal candidate has 5–10 years in CMOS IC design (Analog/Mixed Signal), hands-on Cadence/Virtuoso, Verilog for modeling, and a solid understanding of memory