Senior MEMS Analog Front-End Architect

STMicroelectronics Italia; Cornaredo; On-site; EUR 65,000 - 95,000; Full time

Job summary

STMicroelectronics Italia in Lombardy seeks a brilliant analog FE design engineer to accelerate MEMS IC definition and implementation, collaborating with system architects and cross-functional teams to deliver high-performance inertial sensors.

You will drive transistor-level implementation, verify with simulations, and coordinate with layout engineers for IP layouts and post-layout checks, contributing to product qualification and industrialization.

Qualifications

• 5+ years of experience in analog electronics design.
• Familiarity with industrialization processes and debug/char activities.
• Strong knowledge of low power and low noise design techniques.
• Experience with Spice-based tools and mixed-signal simulation.
• Knowledge of analog blocks modeling (Verilog-A/SystemVerilog).
• System-level block implementation approach is a key skill.
• Proactivity to facilitate cross-functional team discussions.
• MEMS knowledge is a strong plus.

Responsibilities

• Accelerate definition and implementation of IC in MEMS solutions.
• Collaborate with system architect to develop blocks and sub-systems.
• Coordinate with layout engineer to drive IP layout and verify post-layout performance.
• Participate in evaluation and characterization to verify functionality and performance.

Skills

Analog design

Spice-based tools

Verilog-A/SystemVerilog

System-level design

Low noise design

Cross-functional collaboration

MEMS knowledge

Education

Master’s degree in electronic engineering

Tools

Verilog-A

Job description

STMicroelectronics Italia in Lombardy seeks a brilliant analog FE design engineer to accelerate MEMS IC definition and implementation, collaborating with system architects and cross-functional teams to deliver high-performance inertial sensors.

You will drive transistor-level implementation, verify with simulations, and coordinate with layout engineers for IP layouts and post-layout checks, contributing to product qualification and industrialization.