Senior ASIC Design Engineer - Vision Processor & SoCs

VisLab (an Ambarella Inc. company); Parma; On-site; EUR 60,000 - 90,000; Full time

Job summary

VisLab (an Ambarella Inc. company) in Parma, Italy, is seeking a Sr. ASIC Design Engineer to help deliver a next‑generation computer vision processor.

You will design and implement Verilog/SystemVerilog modules for SOCs—image processing logic, vector processors, and device/memory controllers—and drive design integration, synthesis, timing closure and power optimization. Collaborate with a cross‑functional team, contribute to front‑end methodologies and tool flows, and develop a robust, scalable

Qualifications

• Master’s degree in Electrical Engineering.
• 0–4 years of experience.
• Strong knowledge of VLSI/ASIC design and computer architecture.
• Experience with Verilog/SystemVerilog and scripting languages.
• Familiarity with design verification and timing closure.

Responsibilities

• Develop micro-architecture specifications for a next-generation computer vision processor.
• Design and implement Verilog/SystemVerilog modules for SOCs (image processing logic, vector processors, device/memory controllers).
• Perform design integration, synthesis, and optimization for timing, area and power.
• Develop front-end methodologies and tool flows.

Skills

VLSI/ASIC design

Computer architecture

SystemVerilog

Verilog

Python

Design verification

Timing closure

Team player

Education

Master's degree in Electrical Engineering

Tools

Verilog

SystemVerilog

Job description

VisLab (an Ambarella Inc. company) in Parma, Italy, is seeking a Sr. ASIC Design Engineer to help deliver a next‑generation computer vision processor.

You will design and implement Verilog/SystemVerilog modules for SOCs—image processing logic, vector processors, and device/memory controllers—and drive design integration, synthesis, timing closure and power optimization. Collaborate with a cross‑functional team, contribute to front‑end methodologies and tool flows, and develop a robust, scalable