Sr. ASIC Design Engineer

VisLab (an Ambarella Inc. company); Parma; On-site; EUR 60,000 - 90,000; Full time

Job summary

VisLab (an Ambarella Inc. company) in Parma, Italy, is seeking a Sr. ASIC Design Engineer to help deliver a next‑generation computer vision processor.

You will design and implement Verilog/SystemVerilog modules for SOCs—image processing logic, vector processors, and device/memory controllers—and drive design integration, synthesis, timing closure and power optimization. Collaborate with a cross‑functional team, contribute to front‑end methodologies and tool flows, and develop a robust, scalable

Qualifications

• Master’s degree in Electrical Engineering.
• 0–4 years of experience.
• Strong knowledge of VLSI/ASIC design and computer architecture.
• Experience with Verilog/SystemVerilog and scripting languages.
• Familiarity with design verification and timing closure.

Responsibilities

• Develop micro-architecture specifications for a next-generation computer vision processor.
• Design and implement Verilog/SystemVerilog modules for SOCs (image processing logic, vector processors, device/memory controllers).
• Perform design integration, synthesis, and optimization for timing, area and power.
• Develop front-end methodologies and tool flows.

Skills

VLSI/ASIC design

Computer architecture

SystemVerilog

Verilog

Python

Design verification

Timing closure

Team player

Education

Master's degree in Electrical Engineering

Tools

Verilog

SystemVerilog

Job description

We’re growing! Our team in Parma (Italy) is seeking a Sr. ASIC Design Engineer.

Responsibilities:

• Developing micro-architecture specifications for a next generation Computer Vision processor;
• Designing and implementing Verilog/SytemVerilog modules for cutting edge SOCs. Examples of such modules include:
  • Image processing logic
  • Vector processors
  • Device / Memory controllers

• Design integration, logic synthesis, and design optimization for timing, area and power;
• Developing front-end methodologies and tool flows;

Requirements:

• Master’s degree in Electrical Engineering with 0-4 years of experience;
• Very good understanding of VLSI/ASIC design, Computer architecture and Logic design;
• Good knowledge and experience in using hardware description languages (Verilog/SystemVerilog);
• Ability to program in scripting languages, like Python and Perl;
• Knowledge of design verification, and functional coverage;
• Strong communication skills and a good team player;
• Knowledge of logic synthesis and timing closure is a must
• Knowledge and/or experience in the areas of Image/Video processing, computer vision, machine learning are plus;

As an Equal Opportunity/Affirmative Action Employer, Vislab and Ambarella recruit qualified applicants without regard to race, color, national origin, sex, physical disability, or veteran status.

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