MCU Digital Verification Engineer – Edge AI

NXP Semiconductors; Catania; Ibrido; EUR 38.000 - 52.000; Tempo pieno

Descrizione del lavoro

NXP Semiconductors in Catania, Italy, is seeking a digital IC design verification engineer to develop verification environments and test benches using SystemVerilog and UVM. You will collaborate across design, architecture, and software teams to ensure correctness of complex digital circuits.

Requirements include 2+ years in verification, strong SystemVerilog/UVM, and scripting (Python/Perl/Tcl). Fluency in English is essential, and the role is based in Italy with onsite work in Catania.

Competenze

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
• Proven experience (2+ years) in digital IC design verification.
• Strong proficiency in SystemVerilog and UVM (Universal Verification Methodology).
• Experience with Questa, VCS, Xcelium.
• Fluency in English (written and spoken).
• Experience with Python, Perl, or Tcl scripting.
• Familiarity with functional coverage driven verification and assertion-based verification.

Mansioni

• Develop and implement verification environments and test benches using industry-standard methodologies (UVM, SystemVerilog).
• Create detailed verification plans based on design specs, identifying key functionalities and corner cases.
• Develop, execute, and debug test cases to verify the design against specifications.
• Analyze simulation results and collaborate with design engineers to resolve issues.
• Maintain verification collateral, including assertions and coverage models.
• Participate in verification reviews and improve verification flows and tools.
• Document verification strategies, plans, and results effectively.

Conoscenze

SystemVerilog

UVM

Digital IC design verification

Python

Perl

Tcl

English communication

Formazione

Bachelor's or Master's degree in Electrical Engineering or Computer Engineering

Strumenti

Questa

VCS

Xcelium

Descrizione del lavoro

NXP Semiconductors in Catania, Italy, is seeking a digital IC design verification engineer to develop verification environments and test benches using SystemVerilog and UVM. You will collaborate across design, architecture, and software teams to ensure correctness of complex digital circuits.

Requirements include 2+ years in verification, strong SystemVerilog/UVM, and scripting (Python/Perl/Tcl). Fluency in English is essential, and the role is based in Italy with onsite work in Catania.