Senior Physical Design Engineer - Edge MCU Specialist

NXP Semiconductors; Catania; In loco; EUR 61.000 - 84.000; Tempo pieno

Vantaggi offerti da questo lavoro

Annual incentives

Equity

Competitive benefits package

Descrizione del lavoro

NXP Semiconductors in Italy is seeking an experienced Senior Physical Design Engineer to contribute to the physical design and implementation of complex, high‑performance semiconductor ICs, focusing on timing closure, floorplanning, place and route, and power integrity.

You will mentor junior engineers, collaborate with architecture, RTL, DFT and packaging teams, and drive flow improvements and tool adoption to deliver world‑class products.

Competenze

• Bachelor's/Master's degree with substantial industry experience.
• Extensive back-end implementation knowledge including timing, power, synthesis and STA.
• Expertise with top-level design experiences favored.
• Strong proficiency with Cadence/Synopsys/Ansys EDA tools.

Mansioni

• Floorplanning, power grid design, place and route, and timing closure.
• Conduct STA, IR drop and crosstalk analyses and implement solutions.
• Oversee DRC/LVS and physical verification for tape-out readiness.
• Collaborate with architecture, RTL, DFT and packaging teams.
• Mentor junior and senior physical design engineers and drive design flows.

Conoscenze

Physical design

Floorplanning

STA

Power analysis

Timing closure

Scripting (Tcl, Python, Perl)

EDA tools expertise

Mentoring

Formazione

Bachelor's or Master's in Electrical Engineering or related field

Strumenti

Cadence Innovus

Synopsys Fusion Compiler/ICC2

Ansys RedHawk/PowerSI

Synopsys PrimeTime

Synopsys IC Validator

Cadence Pegasus/PVS

Mentor Calibre

Descrizione del lavoro

NXP Semiconductors in Italy is seeking an experienced Senior Physical Design Engineer to contribute to the physical design and implementation of complex, high‑performance semiconductor ICs, focusing on timing closure, floorplanning, place and route, and power integrity.

You will mentor junior engineers, collaborate with architecture, RTL, DFT and packaging teams, and drive flow improvements and tool adoption to deliver world‑class products.