Junior Digital IC Design Engineer (Verilog/SV)

NXP Semiconductors; Catania; Ibrido; EUR 31.000 - 43.000; Tempo pieno

Descrizione del lavoro

NXP Semiconductors is building new teams in Catania to develop high‑impact MCU SOCs and digital IC design. The role focuses on RTL design, Verilog/SystemVerilog, DFT, and collaboration with analog, mixed‑signal, and software teams to ensure performance and quality.

The candidate should have a Master’s in Electrical/Electronics Engineering, strong RTL verification skills, and experience with industry EDA tools. The position involves on‑site work in Italy with a competitive salary and benefits.

Competenze

• Master's degree in Electrical/ Electronics Engineering or related field.
• Expertise in Verilog/SystemVerilog for RTL design and verification.
• Familiarity with EDA tools for RTL coding, synthesis, STA, formal verification.
• Understanding of CDC issues, power integrity, and low‑power design.
• Experience with scripting languages (Python, Perl, Tcl) for automation.
• Strong problem solving and team collaboration skills.
• Ability to take initiative and lead technical discussions.

Mansioni

• Develop digital sub-circuits for SOCs based on predefined specs, RTL coding, synthesis, STA, formal verification, and power analysis.
• Contribute to DFT implementation and verification; debugging.
• Collaborate with analog, mixed-signal, and software teams to define interfaces and optimize system performance.
• Follow team design methodologies to meet schedule and quality targets.
• Perform design verification using simulation, formal verification, and emulation.
• Support post-silicon validation and debugging to ensure product quality.
• Create detailed design documentation and test plans.

Conoscenze

Verilog/SystemVerilog

RTL design

Python

Perl

Tcl

Digital IC design principles

Debugging skills

Formazione

Master's degree in Electrical Engineering

Master's degree in Electronics Engineering

Strumenti

EDA tools

Synthesis

Descrizione del lavoro

NXP Semiconductors is building new teams in Catania to develop high‑impact MCU SOCs and digital IC design. The role focuses on RTL design, Verilog/SystemVerilog, DFT, and collaboration with analog, mixed‑signal, and software teams to ensure performance and quality.

The candidate should have a Master’s in Electrical/Electronics Engineering, strong RTL verification skills, and experience with industry EDA tools. The position involves on‑site work in Italy with a competitive salary and benefits.