Principal Physical Design Engineer - MCU

NXP Semiconductors

Catania

In loco

EUR 61.000 - 84.000

Tempo pieno

3 giorni fa
Candidati tra i primi
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Vantaggi offerti da questo lavoro

Annual incentives
Equity
Competitive benefits package

Descrizione del lavoro

NXP Semiconductors in Italy is seeking an experienced Senior Physical Design Engineer to contribute to the physical design and implementation of complex, high‑performance semiconductor ICs, focusing on timing closure, floorplanning, place and route, and power integrity.

You will mentor junior engineers, collaborate with architecture, RTL, DFT and packaging teams, and drive flow improvements and tool adoption to deliver world‑class products.

Competenze

  • Bachelor's/Master's degree with substantial industry experience.
  • Extensive back-end implementation knowledge including timing, power, synthesis and STA.
  • Expertise with top-level design experiences favored.
  • Strong proficiency with Cadence/Synopsys/Ansys EDA tools.

Mansioni

  • Floorplanning, power grid design, place and route, and timing closure.
  • Conduct STA, IR drop and crosstalk analyses and implement solutions.
  • Oversee DRC/LVS and physical verification for tape-out readiness.
  • Collaborate with architecture, RTL, DFT and packaging teams.
  • Mentor junior and senior physical design engineers and drive design flows.

Conoscenze

Physical design
Floorplanning
STA
Power analysis
Timing closure
Scripting (Tcl, Python, Perl)
EDA tools expertise
Mentoring

Formazione

Bachelor's or Master's in Electrical Engineering or related field

Strumenti

Cadence Innovus
Synopsys Fusion Compiler/ICC2
Ansys RedHawk/PowerSI
Synopsys PrimeTime
Synopsys IC Validator
Cadence Pegasus/PVS
Mentor Calibre

Descrizione del lavoro

NXP's Industrial & IoT Edge solutions range from the smallest MCUs to very high-performance processors to provide real-time insights and efficient automation when performance matters most. NXP's advanced portfolio of edge processing solutions lets developers explore their most innovative ideas with confidence, enabling applications across the autonomous home, industrial automation, and personal electronics. NXP is building new teams in Catania to create high impact micro-controllers (MCU) as part of NXP's intelligent AI at the Edge. This team will include a wide range of engineering talent from analog to SOC digital design. Full product development local will product world class products at a world class pace. This role will contribute to the physical design and implementation of complex, high-performance semiconductor integrated circuits, driving technical solutions in key areas such as static timing closure, floorplanning, place and route, and physical verification. The role also includes mentoring and developing junior engineers, while ensuring the timely delivery of cutting‑edge products across NXP's diverse portfolio.

Your Responsibilities
  • Floorplanning, power grid design, place and route, low power implementation, clock tree synthesis, timing closure, power/signal integrity analysis, physical verification (DRC/LVS/Antenna).
  • Drive the definition and implementation of physical design methodologies, flows, and best practices to optimize performance, power, and area.
  • Perform comprehensive static timing analysis (STA) and ensure all timing constraints are met across various corners and modes.
  • Conduct power integrity (IR drop) and signal integrity (Crosstalk) analysis and implement solutions to mitigate issues.
  • Oversee and perform design rule checking (DRC), layout versus schematic (LVS), and other physical verification steps to ensure tape-out readiness.
  • Collaborate closely with architecture, RTL design, DFT, and package teams to ensure seamless integration and successful product delivery.
  • Mentor and provide technical guidance to junior and senior physical design engineers, fostering a culture of continuous learning and excellence.
  • Evaluate and adopt new EDA tools and technologies to improve design efficiency and quality.
Your Profile
  • Bachelor's degree with 12+ years of professional experience or Master's degree with 10+ years of professional experience.
  • Working knowledge on advance tech nodes 16ff and below is highly desirable.
  • Extensive knowledge and experience in back-end implementation tasks such as (timing & power), synthesis, low power implementation, power analysis, equivalence checking and STA.
  • Experience at top-level will be preferred.
  • Expert-level proficiency with industry-standard EDA tools for physical design (e.g., Cadence Innovus, Synopsys Fusion Compiler/ICC2, Ansys RedHawk/PowerSI).
  • Deep understanding of Static Timing Analysis (STA) concepts, sign-off criteria, and tools (e.g., Synopsys PrimeTime).
  • Strong knowledge of power analysis and optimization techniques (e.g., UPF/CPF, clock gating, power intent).
  • Proven experience with physical verification tools (e.g., Synopsys IC Validator, Cadence Pegasus/PVS, Mentor Calibre).
  • Solid understanding of semiconductor device physics, process technology effects, and DFM/DFY considerations.
  • Proficiency in scripting languages (e.g., Tcl, Python, Perl) for automation of design flows and analysis.
  • Excellent problem-solving, analytical, and debugging skills.
  • Strong communication and interpersonal skills, with the ability to effectively collaborate with cross-functional teams and mentor other engineers.
  • Ability to work independently and take ownership of critical design aspects.

NXP is committed to equal pay for equal work and work of equal value and applies fair, consistent and transparent remuneration practices.

As of the date of this posting, the estimated gross annual base salary range for this position in Italy is between 61,000 € and 83,900 € annually. This range is intended as a guideline. Actual compensation may vary based on qualifications, experience, skills, and specific business or organizational needs. This position falls under the applicable National Collective Labour Agreement (Metalmeccanica Industria).

Where relevant, the total compensation package may also include additional elements such as annual incentive opportunities and/or equity, along with a competitive benefits package.

  • annual incentive opportunities and/or equity
  • competitive benefits package.

More information about NXP in Italy...

NXP Semiconductors N.V. (NASDAQ: NXPI) enables a smarter, safer, and more sustainable world through innovation.

As the world leader in secure connectivity solutions for embedded applications, NXP is pushing boundaries in the automotive, industrial & IoT, mobile, and communication infrastructure markets.

For more information visit www.nxp.com Bright Minds. Bright Futures. We believe that a key component to growing our business is to develop our people. To enable you to grow your career at NXP, we offer online and offline learning opportunities to help you develop some of your core and professional skills.

Commitment At NXP. We recognize NXP is a powerful change agent as we continue to deliver innovative solutions that advance a more sustainable future. We remain steadfast in our commitment to sustainability and making measurable year-on-year progress. Also, we aim to create an inclusive work environment and we will not tolerate racism, discrimination or harassment of any kind. We have programs in place focused on diversity, inclusion and equality.

Thank you for considering a career at NXP. To help you prepare for the different steps in our hiring process, see the following useful advice and tips. Are you already an NXP employee? Do not apply here. Instead, you must apply via our internal career page. Thank you for your interest in supporting our recruitment efforts. Please note that NXP operates under a strict Preferred Supplier List (PSL) for all recruitment activities. Any candidate profiles or resume submitted without a prior written agreement or explicit request from our Talent Acquisition team will be considered unsolicited. Such submissions will be deemed free of any obligations, and no fees will be paid by NXP or any of its affiliates, subsidiaries, or divisions - regardless of whether the candidate is hired, either coincidentally or otherwise. Thank you for your understanding.

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