VLSI - Physical Design Engineer/Senior Engineer

Eteros Technologies; Ahmedabad District; On-site; INR 1,500,000 - 2,500,000; Full time

Benefits offered by this job

Career development opportunities

Medical Benefits

Work on leading-edge technologies

Job summary

A semiconductor technology firm in India seeks a Physical Design Engineer/Senior Engineer to lead a team on advanced mixed-signal chip design. The ideal candidate will have 3-5 years of experience in IC design, with proven capabilities in complex SoC implementations and leading top-level projects. This role offers the chance to work with cutting-edge technology, contribute to serious industry advancement, and enjoy medical benefits and career development opportunities.

Qualifications

• 3-5 years of experience in chip implementation.
• Proven track record with final production tape-outs at 16/14nm, 10nm, or 7nm.
• Knowledge of embedded processors and high-speed interfaces.

Responsibilities

• Lead implementation of complex mixed-signal SoC.
• Build and guide a team of implementation engineers.
• Work with external IP vendors for design integration.

Skills

Analog/Mixed/Custom Signal PNR

Hierarchical Place & Route

Power network architecture design

EDA Tools (Cadence, Mentor, Ansys)

Timing analysis

Digital design

Education

BTech/MTech/PhD

Tools

Cadence (Innovus, Voltus)

Mentor (Calibre)

Ansys (Redhawk, Totem)

Job description

Job Title/Role

Physical Design Engineer/Senior Engineer

Experience Level

4+ Years

Employment Type

Full-time

Job Function

Engineering

Summary

Become a leader on a development team working on an advanced mixed signal chip for a high profile Silicon Valley startup.

This position is for a senior-level Chip Design Lead that will

• Lead the implementation of a complex mixed‑signal SoC
• Build and guide a team of implementation engineers
• Work with external IP vendors to integrate blocks into the design
• Ensure that each aspect of the design meets the specified requirements

Key Qualifications

Technical

• Experience in all phases of the IC design process from RTL‑>GDS2
• Analog/Mixed/Custom Signal PNR experience preferred to help drive partitioning for digital and mixed‑signal SoCs
• Preferably TSMC 7nm PNR sign‑off experience using a full COT flow from RTL/gate to GDS
• Experience in developing PNR methodology/flow to and supporting a larger PD team
• Hierarchical Place & Route experience
• Experience in floorplanning, clock & power network architecture and design
• Experience in UPF/CPF power intent flow – multiple supply domains (bump, deca, power switch placement methods)
• Thorough understanding of digital design, timing analysis, and DFT
• Thorough understanding of LVS/DRC/ERC, EMIR (static & dynamic)
• Knowledge of FCBGA I/O ring layout
• EDA Tools: Cadence (Innovus, Voltus), Mentor (Calibre), Ansys (Redhawk, Totem)

Experience

• BTech/MTech/PhD with 3‑5 years’ experience in chip implementation and 3‑5 years as a top-level.
• Proven track record with multiple successful final production tape‑outs at 16/14nm, 10nm, 7nm preferably 3nm
• Knowledge of and experience with embedded processors
• Knowledge of and experience with high‑speed interfaces and memory controllers
• Ability to contribute to and guide the development process to meet stringent industry segment requirements.
• Experience with automotive‑qualified designs
• Proven ability to deliver results in a very fast‑moving startup environment
• Eager to learn & implement groundbreaking new hardware technology
• Must be able to solve complex problems and independently drive tasks to completion in a timely manner.
• Be able to work under limited supervision and take complete accountability.
• Excellent written and verbal communication skills

What’s in it for you

• Work on leading edge technologies
• An opportunity for career development and growth
• Medical Benefits and more

Seniority level

Mid‑Senior level

Employment type

Full‑time

Job function

Engineering and Design

Industries

Semiconductor Manufacturing