Senior Physical Design Architect

Eximietas Design; Bengaluru; On-site; INR 1,500,000 - 2,000,000; Full time

Job summary

A semiconductor manufacturing firm is seeking a Mid-Senior level Physical Design Engineer to work on advanced node designs (10nm/7nm). The role entails developing methodologies for placement and routing, and providing customer training. Candidates should have over 10 years of experience with mainstream P&R tools and a degree in Electronics or related fields. The position is full-time, located in India, with contact via a provided email for resumes.

Qualifications

• Minimum 10+ years of experience in Physical Design with mainstream P&R tools.
• Solid experience in place & route flow.
• Experience on hierarchical designs and low power implementation is an advantage.

Responsibilities

• Working on 10nm/7nm/5nm designs for deployment.
• Responsible for developing flow and methodology for placement, CTS, and routing.
• Provide training and technical support to customers.

Skills

Placement & Routing

Static Timing Analysis

Physical Verification

Synthesis

Education

Bachelor or Master's Degree in Electronics, Electrical, Telecom or VLSI Engineering

Job description

Job Details

• Experience: 10+ Years
• Locations: Visakhapatnam (India), San Jose (Bay Area), USA, Austin, USA (Eligibility: Valid H1B or candidates already in the U.S.)
• Qualification Required: Minimum 10+ years of experience in Physical Design with mainstream P&R tools; Bachelor or Master's Degree in Electronics, Electrical, Telecom or VLSI Engineering.

Roles and Responsibilities

• Working on 10nm/7nm/5nm or lower node designs with various customers for deployment.
• Expertise in solving customers' problems for critical designs to achieve desired performance, area, and power targets.
• Responsible for developing flow and methodology for performing placement, CTS, and routing.
• Provide training and technical support to customers.

Required Technical and Professional Expertise

• Solid experience in place & route flow (placement guidelines, clock-tree synthesis, routing, timing optimizations). Experience on hierarchical designs and/or low power implementation is an advantage.
• Experience on synthesis, interfacing with RTL and implementation designers to achieve better quality of results.
• Experience on floor plan design, including placement of hard macros, packing, power grid and custom analog routes.
• Experience on static timing analysis related activities (constraints development, parasitic extractions, sign‑off requirements).
• Knowledge of physical verification (DRC/LVS/DFM, chip finishing).

Interested candidates please start sharing your resumes: [e-mail]

Contact: [phone]

Associate VLSI Manager – Talent Acquisition | Visakhapatnam

Seniority Level

• Mid‑Senior level

Employment Type

• Full‑time

Job Function

• Design

Industries

• Semiconductor Manufacturing