Verification Engineer - Ethernet

Modernize Chip Solutions (MCS); Bengaluru; Presencial; INR 2.000.000 - 3.200.000; Jornada completa

Descripción de la vacante

Modernize Chip Solutions (MCS) in Bengaluru seeks an experienced Design Verification Engineer specializing in Ethernet protocol verification, SystemVerilog, and UVM. The role centers on verifying complex networking ASICs/SoCs to ensure functional correctness and silicon quality.

You will develop SV/UVM environments, verify MAC/PCS blocks, create coverage-driven plans, and drive regression and sign-off across RTL, emulation, and post-silicon validation teams.

Formación

• Strong proficiency in SystemVerilog and UVM.
• Hands-on experience with ASIC/SoC design verification.
• Good understanding of Ethernet protocols and networking fundamentals.
• Experience with Ethernet MAC/PCS verification and packet-based interfaces.
• Knowledge of constrained-random verification, functional coverage, assertions, and testbench development.

Responsabilidades

• Develop and maintain SystemVerilog/UVM-based verification environments for Ethernet IPs and networking SoCs.
• Verify Ethernet MAC, PCS, and related networking blocks.
• Develop verification plans, test scenarios, constrained-random tests, and functional coverage models.
• Perform block-level and subsystem-level verification, including integration testing.
• Debug simulation failures, identify root causes, and work closely with RTL design teams.
• Verify Ethernet protocol functionality, packet processing, error handling, and corner cases.
• Develop assertions and coverage-driven verification methodologies.
• Collaborate with architecture, RTL, emulation, and post-silicon validation teams.
• Drive regression execution, coverage closure, and verification sign-off.

Conocimientos

SystemVerilog

UVM

ASIC/SoC verification

Python

Educación

Bachelor's degree in Electronics/Electrical Engineering/Computer Engineering

Herramientas

Python

Perl

Tcl

Descripción del empleo

Role: Design Verification (DV) Engineer – Ethernet

Experience: 7+ years

Job Summary

We are looking for an experienced Design Verification Engineer with strong expertise in Ethernet protocol verification, System Verilog, and UVM. The candidate will be responsible for verifying complex networking ASICs and SoCs, ensuring functional correctness, protocol compliance, and high-quality silicon delivery.

Key Responsibilities

Develop and maintain SystemVerilog/UVM-based verification environments for Ethernet IPs and networking SoCs.

Verify Ethernet MAC, PCS, and related networking blocks.

Develop verification plans, test scenarios, constrained-random tests, and functional coverage models.

Perform block-level and subsystem-level verification, including integration testing.

Debug simulation failures, identify root causes, and work closely with RTL design teams.

Verify Ethernet protocol functionality, packet processing, error handling, and corner cases.

Develop assertions and coverage-driven verification methodologies.

Collaborate with architecture, RTL, emulation, and post-silicon validation teams.

Drive regression execution, coverage closure, and verification sign-off.

Required Technical Skills

Strong proficiency in SystemVerilog and UVM.

Hands-on experience with ASIC/SoC design verification.

Good understanding of Ethernet protocols and networking fundamentals.

Experience with Ethernet MAC/PCS verification and packet-based interfaces.

Knowledge of constrained-random verification, functional coverage, assertions, and testbench development.

Strong debugging skills using simulation tools and waveform analysis.

Experience with scripting languages such as Python, Perl, or Tcl.

Familiarity with regression management and verification metrics.

Preferred Skills

Experience with high-speed Ethernet interfaces such as 10G, 25G, 40G, 100G, 200G, or 400G.

Knowledge of IEEE 802.3 standards.

Exposure to networking protocols, packet switching, and data-center networking.

Experience with SerDes, Ethernet PHY, PCS, or MAC-layer verification.

Familiarity with emulation, FPGA prototyping, or post-silicon validation.

Education

Bachelor’s or Master’s degree in Electronics, Electrical Engineering, Computer Engineering, or a related field.