DV Engineer

Incise Infotech Pvt. Ltd.; Bengaluru; On-site; INR 600,000 - 1,200,000; Full time

Job summary

Incise Infotech Pvt. Ltd. in Bengaluru seeks a verification engineer with expertise in Ethernet protocols and standards. The candidate will create specification-driven verification plans, modify testbenches, and ensure functional and code coverage analysis for Ethernet IP blocks.

Strong experience in SV-UVM for testbench development is essential, as well as the ability to collaborate with design teams for verification. The role requires detailed documentation and regression execution to achieve project milestones.

Qualifications

• Experience in Ethernet protocols and standards (MAC interface – RGMII/RMII/MII, 802.3, 802.1Q etc).
• Strong experience in detailed test plan creation for complex Subsystem and IP's.
• Own regression execution, triage, and debug of failures across RTL.

Responsibilities

• Create detailed, specification-driven verification plans for Ethernet IP blocks.
• Modify existing testbench to suit new requirements.
• Drive functional and code coverage analysis to achieve verification sign-off targets.

Skills

Ethernet protocols and standards

SV-UVM

Testbench development

Debugging and root-cause analysis

Job description

• Experience in Ethernet protocols and standards (MAC interface – RGMII/RMII/MII, 802.3, 802.1Q etc)
• Prior work on Ethernet switching SoCs or Ethernet VIP development
• Create detailed, specification-driven verification plans with clear feature decomposition, coverage goals, and measurable metrics for Ethernet IP blocks and subsystem level
  Architect, develop, reusable testbench components in SV-UVM for a complex data path at IP and Subsystem.
• Modify existing testbench to suit new requirements
• Strong experience in detailed test plan creation for complex Subsystem and IP’s
• Full constrained random test case development at Subsystem level
• Own regression execution, triage, and debug of failures across RTL, testbench, and interface interactions. Perform root-cause analysis and drive resolution in close partnership with design engineers.
• Drive functional and code coverage analysis to achieve verification sign-off targets. Identify coverage holes, develop targeted tests, and track progress to closure
• Actively participate in specification reviews, design reviews, and verification plan reviews. Collaborate closely with RTL designers, architects, and cross-functional teams to understand design intent and identify verification gaps
• Maintain thorough documentation of verification environments, test plans, coverage reports, and known issues for project tracking and knowledge transfer