Senior DV Engineer

Incise Infotech Pvt. Ltd.; Bengaluru; On-site; INR 1,000,000 - 1,500,000; Full time

Job summary

Incise Infotech Pvt. Ltd. is looking for a candidate with a robust background in Ethernet protocols and verification methodologies. You will create detailed verification plans, develop reusable testbench components in SV-UVM, and ensure thorough coverage analysis for verification sign-off.

The ideal candidate will possess strong experience with Ethernet switching SoCs and thorough documentation skills. Collaboration with cross-functional teams is essential to identify and close verification gaps.

Qualifications

• Experience with Ethernet protocols (e.g., MAC interface – RGMII/RMII/MII).
• Strong background in Ethernet switching SoCs or VIP development.
• Ability to create detailed, specification-driven verification plans.

Responsibilities

• Develop reusable testbench components in SV-UVM for complex data paths.
• Conduct regression execution and debug failures across RTL.
• Drive functional and code coverage analysis for verification sign-off.

Skills

Ethernet protocols and standards

UVM testbench development

Test plan creation

Root-cause analysis

Tools

Coverage management tools

Job description

• Experience in Ethernet protocols and standards (MAC interface – RGMII/RMII/MII, 802.3, 802.1Q etc)
• Prior work on Ethernet switching SoCs or Ethernet VIP development
• Create detailed, specification-driven verification plans with clear feature decomposition, coverage goals, and measurable metrics for Ethernet IP blocks and subsystem level
  Architect, develop, reusable testbench components in SV-UVM for a complex data path at IP and Subsystem.
• Modify existing testbench to suit new requirements
• Strong experience in detailed test plan creation for complex Subsystem and IP’s
• Full constrained random test case development at Subsystem level
• Own regression execution, triage, and debug of failures across RTL, testbench, and interface interactions. Perform root-cause analysis and drive resolution in close partnership with design engineers.
• Drive functional and code coverage analysis to achieve verification sign-off targets. Identify coverage holes, develop targeted tests, and track progress to closure
• Actively participate in specification reviews, design reviews, and verification plan reviews. Collaborate closely with RTL designers, architects, and cross-functional teams to understand design intent and identify verification gaps
• Maintain thorough documentation of verification environments, test plans, coverage reports, and known issues for project tracking and knowledge transfer
• Exposure to register verification using UVM RAL
• Experience with coverage management tools