Ethernet Verification Engineer

LeadSOC Technologies Pvt Ltd; Bengaluru; In loco; INR 2.200.000 - 2.800.000; Tempo pieno

Descrizione del lavoro

LeadSOC Technologies Pvt Ltd in Bengaluru is seeking a Design Verification Engineer specialized in Ethernet to drive protocol compliance tasks across Ethernet IP/SoC projects, ensuring robust Ethernet IP performance in next‑gen silicon.

The role requires hands-on Ethernet protocol compliance / CTS coverage closure experience, strong debugging skills, ability to analyze logs, waveforms and protocol traces, and collaboration with RTL Design, Verification, Validation and Firmware teams.

Competenze

• 5+ years in design verification of Ethernet IP/SoC
• 2+ years in Ethernet Protocol Compliance / CTS
• Experience with CTS execution and coverage closure
• Proficient in failure analysis and protocol debugging
• Experience with logs, waveforms, protocol traces and test results
• Strong understanding of Ethernet packet structure and compliance

Mansioni

• Analyze logs, waveforms and protocol traces to identify failures
• Collaborate with RTL Design, Verification, Validation and Firmware teams for debug
• Develop and debug test cases; support regression and coverage analysis
• Drive CTS coverage closure and compliance verification
• Utilize SystemVerilog/UVM methodologies in verification

Conoscenze

Ethernet verification

CTS coverage closure

Failure analysis

Protocol debugging

SystemVerilog/UVM

Strumenti

SystemVerilog

UVM

Waveform analysis

Python

C/C++

Descrizione del lavoro

Job Description – Ethernet Protocol Compliance / CTS Engineer

Design Verification Engineer – Ethernet

Experience: 5+ Years

Domain: Ethernet / SoC / IP Verification

Job Description:

• Strong hands-on experience in Design Verification of Ethernet IP/SoC.
• Minimum 2+ years of experience in Ethernet Protocol Compliance / CTS execution and coverage closure.
• Experience in executing and analyzing Ethernet Compliance Test Suites (CTS) and driving coverage closure.
• Strong expertise in failure analysis, protocol-level debugging, root-cause analysis, and issue closure.
• Analyze logs, waveforms, protocol traces, and test results to identify and resolve failures.
• Good understanding of Ethernet packet structure, protocol behavior, and compliance requirements.
• Work closely with RTL Design, Verification, Validation, and Firmware teams for debug and issue resolution.
• Develop/debug test cases and support regression, coverage analysis, and compliance closure.
• Experience with SystemVerilog/UVM and verification methodologies is preferred.

Good to Have:

• Experience with 10G/25G/40G/100G/200G/400G Ethernet.
• Knowledge of IEEE 802.3, Ethernet MAC/PCS/PHY.
• Experience with protocol analyzers, traffic generators, and Ethernet validation tools.
• Scripting/programming knowledge in Python, C/C++ or Shell.

Key Requirement:

Candidates must have hands-on Ethernet Protocol Compliance / CTS Coverage Closure experience, not just generic Ethernet testing or validation exposure.

Immediate joiners are strongly preferred.