Technical Staff Engineer - Verification

FHLB Des Moines; Hyderabad; On-site; INR 3,500,000 - 5,500,000; Full time

Job summary

Microchip Technology Inc. in Hyderabad is seeking an experienced Ethernet Protocol Verification Engineer to develop and execute verification strategies for Ethernet MAC, PCS and PHY for our next generation of FPGA.

You will define verification specifications, develop comprehensive verification plans, and drive hands-on simulation-based functional verification using SystemVerilog/UVM. Mentoring engineers and collaborating across functions are included.

Qualifications

• 12+ years of functional verification experience in Ethernet 40G/100G and related protocols.
• Strong knowledge of Ethernet and AMBA AXI/AHB protocols.
• Proficiency in SystemVerilog/UVM testbench development and debugging.

Responsibilities

• Define verification specifications and plans for Ethernet MAC/PCS/PHY.
• Develop robust UVM testbenches and coverage models.
• Execute regression suites and drive closure of verification goals.

Skills

Ethernet 40G/100G

AMBA AXI/AHB

SystemVerilog/UVM

Python scripting

Verification methodologies

HDL languages

C-based test development

Education

Bachelor's or Master's in Electrical Engineering

Tools

SystemVerilog/UVM

Job description

Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology Inc. People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the Aggregate System and it’s won us countless awards for diversity and workplace excellence. Our company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you.

Job Description:

About the Role

We are seeking an experienced Ethernet Protocol Verification Engineer to develop and execute verification strategies for Ethernet MAC, PCS and PHY for our next generation of FPGA. In this role, you will define verification specifications, develop comprehensive verification plans, and drive hands‑on simulation‑based functional verification using industry‑standard methodologies such as System Verilog and UVM. You will independently manage challenging verification activities, debug RTL against design intent, and collaborate closely with cross‑functional teams to ensure successful project outcomes. Hands‑on project experience with leading‑edge verification methodologies such as OVM/UVM is required. This role requires strong expertise in Ethernet standard, packet‑based verification, and hardware/software debug skill This role also includes mentoring engineers, sharing best practices, and contributing to a culture of technical excellence, innovation, and continuous improvement.

Requirements/Qualifications:

Bachelor’s or Master’s degree in Electrical Engineering or a related field.

Required Skills and Experience

• 12+ years of functional verification experience, with strong hands‑on verification expertise in Ethernet 40G/100G, 1588 PTP, JESD204 simulation verification.
• Strong protocol knowledge of Ethernet and AMBA AXI/AHB protocols.
• Strong scripting skills in Python, Shell, Perl, and TCL.
• Experience with coverage‑driven and assertion‑based verification methodologies.
• Experience developing constrained‑random and directed simulation testcases using System Verilog/UVM; knowledge of C‑based testcase development is a plus.
• Solid understanding of IC chip design, development flows, and verification methodologies.
• Proficiency in HDL languages, including System Verilog, Verilog, and VHDL.
• Proven ability to develop verification plans, build robust UVM testbenches, define functional coverage models, execute regressions, analyze coverage gaps, and drive closure against verification goals.

Travel Time: 0% - 25%