Lead Design Verification Engineer

LeadSOC Technologies Pvt Ltd; Bengaluru; Sur place; INR 1 800 000 - 2 800 000; Plein temps

Résumé du poste

LeadSOC Technologies Pvt Ltd in Bengaluru seeks a Lead Design Verification Engineer with 6-12 years of ASIC/SoC verification experience. You will lead IP/SoC verification, drive SystemVerilog/UVM environments, and define test plans for PCIe and Ethernet interfaces while mentoring junior engineers.

Strong hands-on SystemVerilog/UVM, PCIe/Ethernet proficiency, and leadership are essential to drive sign-off and methodology improvements across RTL, Architecture, Firmware, and Physical Design teams.

Qualifications

• 6-12 years ASIC/SoC Design Verification experience.
• Strong hands-on expertise in SystemVerilog and UVM.
• Strong experience in PCIe and Ethernet protocol verification.
• Experience with IP, subsystem and SoC-level verification.
• Good understanding of high-speed protocols, SoC architecture and IP integration.
• Experience with verification planning, regression and sign-off.

Responsabilités

• Lead IP and SoC-level verification for complex ASIC designs.
• Develop scalable SystemVerilog/UVM-based verification environments.
• Define verification strategy, test plans, coverage goals and sign-off criteria.
• Drive functional verification of PCIe and Ethernet interfaces/protocols.
• Develop constrained-random tests, sequences, scoreboards, monitors and functional coverage.
• Debug complex simulation failures using VCS/Verdi or equivalent tools.
• Drive functional and code coverage closure and verification sign-off.
• Work closely with RTL, Architecture, Firmware, DFT and Physical Design teams.
• Develop reusable verification components and improve verification methodologies.
• Mentor junior engineers and provide technical leadership.

Connaissances

SystemVerilog

UVM

PCIe

Ethernet

Leadership

Scripting (Python/Perl/Tcl)

Verification planning

Outils

VCS/Verdi

Description du poste

Lead Design Verification Engineer - PCIe / Ethernet

Experience: 6-12 Years

Role Overview

We are looking for a Lead Design Verification Engineer with strong hands-on expertise in SystemVerilog, UVM, PCIe and Ethernet to drive IP and SoC-level verification for complex, high-performance designs.

Key Responsibilities

• Lead IP and SoC-level verification for complex ASIC designs.
• Develop scalable SystemVerilog/UVM-based verification environments.
• Define verification strategy, test plans, coverage goals and sign-off criteria.
• Drive functional verification of PCIe and Ethernet interfaces/protocols.
• Develop constrained-random tests, sequences, scoreboards, monitors and functional coverage.
• Debug complex simulation failures using VCS/Verdi or equivalent tools.
• Drive functional and code coverage closure and verification sign-off.
• Work closely with RTL, Architecture, Firmware, DFT and Physical Design teams.
• Develop reusable verification components and improve verification methodologies.
• Mentor junior engineers and provide technical leadership.

Required Skills

• 6-12 years of ASIC/SoC Design Verification experience.
• Strong hands-on expertise in SystemVerilog and UVM.
• Strong experience in PCIe and Ethernet protocol verification.
• Experience with IP, subsystem and SoC-level verification.
• Good understanding of high-speed protocols, SoC architecture and IP integration.
• Experience with VCS/Verdi, assertions and functional coverage.
• Strong debugging and scripting skills using Python/Perl/Tcl.
• Experience in verification planning, regression and sign-off.
• Strong communication and technical leadership skills.