Verification Engineer - 2420

Sunrise Biztech Systems; Bengaluru; On-site; INR 3,000,000 - 6,000,000; Full time

Job summary

Sunrise Biztech Systems in Bengaluru is seeking a Verification Engineer with 9+ years of experience to develop and enhance SystemVerilog/UVM-based testbenches for complex client/server interconnects.

You will interact with architects and RTL designers to deepen expertise in the Infinity Fabric architecture and contribute to post-silicon validation efforts. Mentoring junior engineers is part of the role.

Qualifications

• 9+ years of verification experience.
• Strong SystemVerilog/UVM/verification skillset.
• Experience with ASIC verification at IP/subsystem level.
• Mentoring junior engineers.

Responsibilities

• Develop and enhance SystemVerilog/UVM-based testbenches to verify features for client/server/graphics/interconnects.
• Collaborate with architects, RTL designers, performance engineers, and post-silicon validation engineers to gain deep expertise in Infinity Fabric architecture.
• Understand TestBench Architecture and develop expertise in TestBench Verification Components.
• Mentor junior engineers.

Skills

SystemVerilog

UVM

TestBench Verification

Mentoring

Education

Bachelor's or Master's in Electronics/EE/CE

Tools

Scripting (Perl/Ruby/Make)

Job description

Position: Verification Engineer

Experience: 9+ Years

Location: Bengaluru

Contract tenure: 12 months

KEY RESPONSIBILITIES:

• Develop and enhance System Verilog / UVM-based testbenches to verify new features for client, server, graphics, and semi-custom interconnects.
• Interact with architects, RTL designers, performance engineers, and post-silicon validation engineers to develop deep expertise in the Infinity Fabric architecture.
• Understand TestBench Architecture and develop expertise in TestBench Verification Components.
• Mentor junior engineers.

PREFERRED EXPERIENCE:

• Proficient in IP or Subsystem level ASIC verification
• Architected and developed complex verification environments and infrastructure, including scripting using Perl, Ruby, Make, or similar.
• Exposure to RTL design, software development, formal verification, or other related domains.
• Experience in UVM TestBench Development for complex designs preferred.
• Industry experience is preferred.

ACADEMIC CREDENTIALS:

• Bachelors or masters degree in Electronics or Electrical or Computer engineering