IP verification engineer - 2319

Sunrise Biztech Systems; Hyderabad; On-site; INR 2,500,000 - 4,500,000; Full time

Job summary

Sunrise Biztech Systems Pvt. Ltd. in Hyderabad is hiring for an IP verification Engineer with 8-10 years of experience to work on FPGA/ASIC verification projects for a leading semiconductor client.

You will collaborate with architecture, IP design, PD teams and product engineers to ensure first pass silicon success, develop UVM testbenches, and run regressions across PCIe and CXL based IPs.

Qualifications

• 8–10 years experience in IP verification.
• Strong Verilog/SystemVerilog and UVM expertise.
• Experience with PCIe/CXL/ Ethernet protocols preferred.

Responsibilities

• Collaborate with architects, hardware engineers, and firmware engineers to understand features to verify for PCIe/CXL based IPs.
• Develop test plan documentation considering interactions with hardware, firmware, and software drivers.
• Code IP or SS level UVM based testbenches, verification components, monitors, scoreboard, checkers.
• Build directed and random verification tests.
• Run regressions and debug test failures to ensure high design quality.

Skills

Verilog

SystemVerilog

UVM

IP verification

PCIe verification

CXL verification

Python scripting

Testbench development

Tools

UVM framework

Job description

Urgent Hiring!!!

Greetings from Sunrise Biztech Systems Pvt. Ltd.

We are hiring for one of our top leading semiconductor client. If you're interested and your experience matches the requirement, we'd love to hear from you.

Position: IP verification Engineer
Experience: 8-10 Years

Location: Hyderabad

Contract tenure: 9 months

THE ROLE:

As an IP verification engineer you will help bring to life cutting-edge FPGA, ASICs for variety of target customers.As a member of the front-end design/integration team, you will work closely with the architecture, IP design, PD teams, and product engineers to achieve first pass silicon success.

THE PERSON:

You have a passion for modern, complex IP architectures, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/time zones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.

KEY RESPONSIBLITIES:

• Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified for PCIe CXL based IP's
• Develop test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases
• Code IP or SS level UVM based testbenches, verification components - monitors, scoreboard, checkers
• Build the directed and random verification tests
• Run regressions, debug test failures towards ensuring high design functional, performance and implementation quality

PREFERRED EXPERIENCE:

• Experience with PCIe or CXL or ethernet protocols is preferred
• Proficient in IP level ASIC verification
• Expert in Verilog, System Verilog, Object Oriented programming
• Expertise in developing UVM based verification frameworks and testbenches
• Scripting and automation of verification processes and flows
• Exposure to leadership or mentorship is an asset
• Experience working in a team environment through the ASIC / FPGA Project lifecycle from Planning to Tape Out
• Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process
• Comfortable in python / perl and editing / maintaining scripts
• Strong communication skills and the ability to work independently as well as in a cross-site team environment
• Good Computer Architecture, systems knowledge is a plus
• Exposure to generative AI or simulation tools for test, testbench, assertion, test plan generation or performance optimization is a plus