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Qbit Labs in Gurgaon or Hyderabad is seeking a Verification Engineer to drive SystemVerilog/UVM based verification for RTL IPs. You will develop verification IPs, test environments, and ensure complete coverage.
The role requires strong SystemVerilog/UVM knowledge, experience with Questa/NCsim, and creating constraints, checkers, scoreboards, and assertions. You will write automation scripts for regression and analyze results to improve coverage.
Qbit Labs is an R&D company offering design solutions and services in the wired and wireless communication fields, catering to defense, aerospace, and space-grade products. It has deep expertise in the design of protocol analyzers/exercisers for PCIe, CXL, MIPI, Ethernet, TSN, etc. Thanks to its strong scientific research and innovation, the company holds a niche and strong product portfolio in each operation domain.
We are looking for a Verification Engineer for our Gurgaon or Hyderabad Location. The job requires good knowledge of System Verilog and UVM. Development of Verification IP and Verification test environments for RTL IPs based on System Verilog/UVM. Understand the Specifications and make a Verification Plan that covers the complete Test environment, Test-cases, Test Plan and Coverage. Develop checkers in constrained-random and or directed verification environments using System Verilog/UVM. Usage of assertions for verification. Write scripts for automation and regression and analysis of test results.
Experience: 1 to 5 years
Job Domain: Telecommunication/ Image Processing/ wireless/ protocols
Job Type: Permanent