Verification Engineer (I3C_MASTER) -- Bangalore

MAXVY Technologies Pvt Ltd; Bengaluru; On-site; AUD 12,048 - 18,072; Full time

Job summary

MAXVY Technologies Pvt Ltd in Bangalore seeks a Verification Engineer (I3C_MASTER) with strong SystemVerilog and UVM expertise to verify digital designs and develop test benches from scratch. The role focuses on constructing test plans, sequences, and assertions to ensure functional coverage and performance.

The candidate should be adept at working with APB/I2C/I3C protocols and be a quick learner, ready to collaborate with a dynamic team on challenging projects.

Qualifications

• SV/UVM knowledge is required and experience with verification environments is expected.
• Ability to create test plans and build test benches from scratch.
• Familiarity with APB/I2C/I3C protocols and functional coverage.

Responsibilities

• Create test bench environment from scratch.
• Create sequences as per requirement.
• Create assertion & functional coverage.
• Verify and validate digital designs.

Skills

SV/UVM

Test bench design

Test plan creation

Sequences

Assertions

Functional coverage

APB/I2C/I3C

Quick learner

Education

B.E./B.Tech

M.E./M.Tech

Job description

Verification Engineer (I3C_MASTER)

Location: Bangalore

Experience: 1 Year

Education: B.E, M.E, M.Tech, B.Tech

Role

We are looking for a motivated Verification Engineer with a strong understanding of System Verilog (SV) and UVM methodologies. This is an excellent opportunity for a quick learner who is passionate about creating test plans and building testbench environments from scratch. You will work closely with our team to verify and validate digital designs, ensuring they meet the required functionality and performance standards.

Skill set

• Strong knowledge in SV/UVM
• Quick learner
• Capable of creating test plan.
• Capable of creating test bench environment from scratch.
• Capable of creating sequence as per requirement.
• Capable of creating assertion & functional coverage.
• Strong knowledge of APB / I2C / I3C Protocol.

Responsibilities

• Create test bench environment from scratch.
• Create sequences as per requirement.
• Create assertion & functional coverage.
• Verify and validate digital designs.

Salary: Open to discussion