Senior Static Timing Analysis (STA) Engineer

LeadSoc Technologies Pvt Ltd; Bengaluru; On-site; INR 2,000,000 - 3,800,000; Full time

Job summary

LeadSoc Technologies Pvt Ltd is seeking an STA Engineer to own timing sign-off and closure for complex ICs/SoCs. You will define and validate timing constraints, perform MMMC timing analysis across PVT, and collaborate with design teams to meet target frequency.

You will develop and maintain SDCs, automate reports, and deliver final timing sign-off collateral for tape-out, while identifying critical paths and mitigating Setup/Hold violations.

Qualifications

• 3–8 years of STA experience.
• Proficiency with industry-standard EDA tools.
• Bachelor's or Master's in EE/Electronics/VLSI.

Responsibilities

• Own timing sign-off and closure for ICs/SoCs.
• Develop, validate, and maintain SDCs and timing constraints for all modes.
• Perform MMMC timing analysis across PVT and modes.
• Identify critical paths and resolve Setup/Hold violations.
• Automate STA tasks and generate timing reports.
• Produce final timing reports and sign-off collateral for tape-out.

Skills

STA

Timing analysis

Scripting

Debugging

Education

Bachelor's or Master's in Electrical/Electronics/VLSI

Tools

Fusion Compiler

ICC2

PrimeTime

Innovus

Mentor Graphics

Job description

The Static Timing Analysis (STA) Engineer will own the timing sign-off and closure for complex integrated circuits (ICs) and/or System-on-Chips (SoCs). This role involves defining and validating timing constraints, performing multi-mode multi-corner (MMMC) timing analysis, and collaborating with design and physical design teams to achieve the target operating frequency and performance metrics.

Key Responsibilities

• Timing Sign-off and Analysis
• Timing Closure Ownership: Drive all aspects of timing closure from pre-layout to post-layout for blocks, sub-systems, and/or the full chip.
• Constraint Management: Develop, validate, and maintain Synopsys Design Constraints (SDC) and timing constraints for all functional and test modes (e.g., Scan, MBIST).
• MMMC Analysis: Perform comprehensive timing analysis across multiple operating corners (Process, Voltage, Temperature - PVT) and various modes (Multi-Mode Multi-Corner).
• Critical Path Identification: Analyze timing reports to identify and debug critical paths and resolve all Setup and Hold violations.
• Signal Integrity (SI) & Noise: Incorporate advanced timing effects such as on-chip variation (OCV), signal integrity (crosstalk), and voltage drop (IR-drop aware STA) into the sign-off process.

Methodology and Flow

• Develop, maintain, and enhance STA flows and methodologies to improve efficiency, robustness, and reduce analysis runtime.
• Automate repetitive tasks and report generation using scripting languages.
• Generate final timing reports and sign-off collateral for tape-out.

Education

• Bachelor's or Master's degree in Electrical Engineering (EE), Electronics Engineering, VLSI, or a related field.

Technical Skills & Experience

• Experience: 3 to 8 years of experience in STA.
• EDA Tools: Expert proficiency with industry-standard Electronic Design Automation (EDA) tools from vendors like Synopsys (e.g., Fusion Compiler, ICC2, Primetime), Cadence (e.g., Innovus), or Mentor Graphics.

Soft Skills

• Excellent analytical, debugging, and problem-solving skills.
• Strong verbal and written communication skills.

Ability to work effectively in a team environment and collaborate across different engineering disciplines.