STA Architect

LeadSoc Technologies Pvt Ltd; Bengaluru; On-site; INR 4,000,000 - 7,000,000; Full time

Job summary

LeadSoc Technologies Pvt Ltd is seeking an experienced STA architect to own full-chip timing analysis and signoff across complex SoCs and advanced nodes. You will define timing closure strategies, lead timing budgets, and mentor teams to enable first-pass silicon success.

The role requires deep expertise in PrimeTime/Tempus, ECO implementation, and multi-corner/signoff methodologies, with strong scripting for automation. Collaboration across RTL, Synthesis, PD, and Clocking is essential.

Qualifications

• 12–18 years of hands-on STA experience in large SoCs.
• Expertise in PrimeTime and Tempus for timing signoff.
• Experience with advanced technology nodes (7nm/5nm/3nm).
• Scripting skills in Tcl, Python, or Perl for automation.
• Strong understanding of RTL, Synthesis, and Physical Design flows.

Responsibilities

• Own full-chip STA signoff from synthesis to tapeout across corners.
• Define timing closure strategies for high-performance SoCs.
• Lead timing budgeting and ECO implementation.
• Drive closure of setup/hold, SI, Crosstalk, and timing exceptions.
• Collaborate with RTL, Synthesis, PD, Clocking, and Power teams.

Skills

Static Timing Analysis

PrimeTime

Tempus

Scripting: Tcl

Scripting: Python

Scripting: Perl

Tools

Primetime

Tempus

Job description

Lead the Static Timing Analysis (STA) strategy and signoff for complex SoCs across advanced technology nodes. Drive timing architecture, methodology, and convergence to enable first-pass silicon success.

What You'll Do

• Own full-chip STA signoff from synthesis to tapeout across multiple voltage, process, and mode corners.
• Define and drive timing closure strategies for high-performance, low-power SoCs.
• Lead timing budgeting, hierarchical STA, ECO implementation, and signoff methodology.
• Drive closure of setup/hold, SI, Crosstalk, OCV/AOCV/POCV, CRPR, MMMC, and timing exceptions.
• Collaborate with RTL, Synthesis, Physical Design, Clock, Power, and Architecture teams to resolve timing bottlenecks.
• Develop automation and methodologies to improve timing convergence, QoR, and signoff efficiency.
• Mentor technical teams and provide architectural guidance on timing closure.

What You Bring

• 12–18 years of hands-on experience in Static Timing Analysis for large SoCs.
• Strong expertise in PrimeTime, Tempus, and timing signoff methodologies.
• Deep understanding of MMMC, SI, Crosstalk, OCV/AOCV/POCV, CRPR, ECO, SDC, CTS, and timing constraints.
• Experience with advanced technology nodes (7nm/5nm/3nm or below) and FinFET designs.
• Strong scripting skills in Tcl, Perl, or Python for automation.
• Solid understanding of RTL, Synthesis, Physical Design, Clocking, Power Intent (UPF), CDC/RDC, and low-power implementation.

Preferred

• Experience in CPU, GPU, AI/ML, Networking, Automotive, or High-Performance Compute SoCs.
• Exposure to EMIR, Power Integrity, and Physical Signoff flows.
• Proven experience leading timing closure across multiple tapeouts and mentoring STA teams.

We're Looking For

Engineers who can architect timing methodologies, solve the most challenging timing closure problems, and lead signoff for next-generation high-performance SoCs while raising the technical bar across the organization.