Technical Architect - SoC, Verilog, UVM, C, C++

HCL Technologies Limited; India; On-site; INR 2,500,000 - 4,000,000; Full time

Job summary

HCL Technologies Limited is seeking a Technical Architect for SoC verification in India. The role focuses on scalable DV environments, UVM-based testbenches, and end-to-end verification of ASIC/SoC designs.

You will collaborate with design, architecture, and physical teams to ensure first-time-right silicon. Required expertise includes SystemVerilog, UVM, functional coverage, SVA assertions, and experience with EDA tools.

Qualifications

• BS/MS in Electronics or related field with strong verification knowledge.
• Hands-on experience with SystemVerilog/UVM environments and testbenches.
• Familiarity with EDA tools and coverage-driven verification.

Responsibilities

• Develop and execute comprehensive verification plans from specs.
• Build and maintain SystemVerilog/UVM based verification environments.
• Create reusable testbenches, agents, scoreboards, and checkers.
• Develop directed and constrained-random testcases.
• Perform functional, code, and assertion coverage closure.
• Debug RTL/testbench issues across flows; root-cause analysis.
• Develop and integrate SVA assertions and formal checks.
• RTL and gate-level simulations; automate regression flows.

Skills

SystemVerilog

UVM

Functional coverage

Assertions (SVA)

EDA tools

RTL debugging

Protocols (AXI/PCIe)

Python/Perl/Shell scripting

Education

B.Tech / M.Tech in Electronics / Electrical / CSE

Tools

VCS

Verdi

Job description

Technical Architect - SoC, Verilog, UVM, C, C++ - India

Job Summary

Job Summary

We are seeking skilled Design Verification (DV) Engineers to validate complex ASIC/SoC/IP designs. The role involves developing scalable verification environments, creating test plans, and ensuring functional correctness through advanced verification methodologies such as UVM.

You will work closely with design, architecture, and physical design teams to deliver first-time-right silicon.

Key Responsibilities

Key Responsibilities

• Develop and execute comprehensive verification plans based on design specifications
• Build and maintain SystemVerilog/UVM-based verification environments
• Create reusable testbenches, agents, scoreboards, and checkers
• Develop directed and constrained-random testcases
• Perform functional, code, and assertion coverage closure
• Debug failures and root-cause issues across RTL, testbench, and tools
• Develop and integrate assertions (SVA) and formal checks where applicable
• RTL as well as Gate level simulations
• Automate regression flows and improve verification productivity

Skill Requirements

Technical Skills

• Strong expertise in SystemVerilog
• Hands-on experience with UVM (Universal Verification Methodology)
• Experience with functional coverage, assertions (SVA), and constrained random verification
• Familiarity with EDA tools (e.g., VCS, Verdi)
• Experience in debugging RTL and simulation issues
• Understanding of protocols such as AXI, AHB, APB, PCIe, or similar

Programming/Scripting

• Proficiency in Python/Perl/Shell scripting for automation

Other Requirements

Preferred Qualifications

• Experience in UCIe protocol
• Experience in verifying mixed signal (analog + digital) IPs

Education

• B.Tech / M.Tech in Electronics / Electrical / Computer Engineering or equivalent

Soft Skills

• Strong analytical and debugging skills
• Good communication and cross-functional collaboration
• Ability to work in a fast-paced, tapeout-driven environment

Why HCLTech?

At HCLTech, you'll supercharge your potential. You'll find your career. And you'll find your spark. All at a place that knows that helping its customers stay on top starts by putting its people first.

HCLTech is a global technology company, home to more than 223,000 people across 60 countries, delivering industry-leading capabilities centered around digital, engineering, cloud and AI, powered by a broad portfolio of technology services and products. We work with clients across all major verticals, providing industry solutions for Financial Services, Manufacturing, Life Sciences and Healthcare, Technology and Services, Telecom and Media, Retail and CPG, and Public Services. Consolidated revenues as of 12 months ending June 2026totaled $14.8billion.