Senior Design Lead

HCL Technologies Limited; Bengaluru; On-site; INR 2,000,000 - 3,600,000; Full time

Job summary

HCL Technologies Limited is seeking an experienced SoC Verification Engineer to lead verification planning, execution, and collaboration across Design, DFT, Firmware, and Architecture teams. The role emphasizes integration of IPs/UVCs/VIPs, coverage closure, and power-aware verification in a fast-paced environment.

The candidate will drive RTL and protocol debugging, RAL modeling, and test-chip signoff while leveraging JTAG, DAC, and mixed-signal verification expertise.

Qualifications

• Strong expertise in SystemVerilog, UVM, and SoC verification methodologies.
• Experience in testbench bring-up, SoC integration, and coverage-driven verification.
• Hands-on experience in RAL modeling and RAL-based register verification, including register access, mirroring, prediction, and functional coverage.
• Hands-on experience with UPF-based low-power verification and GLS debugging.
• Knowledge of JTAG, DAC, and analog/mixed-signal model verification.
• Strong debugging, automation, and stakeholder management skills.

Responsibilities

• Develop and execute SoC-level verification plans, testcases, and coverage models to validate subsystem interactions, system functionality, and integration requirements.
• Integrate IPs, UVCs, and VIPs into the SoC verification environment.
• Drive functional/code coverage closure, power-aware verification, and Gate-Level Simulations (GLS).
• Perform debug of RTL, integration, protocol issues.
• RAL Modeling and verification.
• Own test-chip verification and collaborate with Design, DFT, Firmware, and Architecture teams for verification signoff.

Skills

SystemVerilog

UVM

SoC verification

Testbench bring-up

Coverage-driven verification

RAL modeling

Register verification

GLS debugging

Automation

Tools

UPF

GLS

Job description

Responsible for SoC level verification of DDR, driving verification execution, integration, coverage closure, low-power verification, GLS, and test-chip validation activities.

Key Responsibilities

• 1. Develop and execute SoC-level verification plans, testcases, and coverage models to validate subsystem interactions, system functionality, and integration requirements.
• 2. Integrate IPs, UVCs, and VIPs into the SoC verification environment.
• 3. Drive functional/code coverage closure, power-aware verification, and Gate-Level Simulations (GLS).
• 4. Perform debug of RTL, integration, protocol issues.
• 5. RAL Modeling and verification.
• 6. Own test-chip verification and collaborate with Design, DFT, Firmware, and Architecture teams for verification signoff.

Skill Requirements

• 1. Strong expertise in SystemVerilog, UVM, and SoC verification methodologies.
• 2. Experience in testbench bring-up, SoC integration, and coverage-driven verification.
• 3. Hands-on experience in RAL modeling and RAL-based register verification, including register access, mirroring, prediction, and functional coverage.
• 4. Hands-on experience with UPF-based low-power verification and GLS debugging.
• 5. Knowledge of JTAG, DAC, and analog/mixed-signal model verification.
• 6. Strong debugging, automation, and stakeholder management skills.

At HCLTech, you'll supercharge your potential. You'll find your career. And you'll find your spark. All at a place that knows that helping its customers stay on top starts by putting its people first.

HCLTech is a global technology company, home to more than 223,000 people across 60 countries, delivering industry-leading capabilities centered around digital, engineering, cloud and AI, powered by a broad portfolio of technology services and products. We work with clients across all major verticals, providing industry solutions for Financial Services, Manufacturing, Life Sciences and Healthcare, Technology and Services, Telecom and Media, Retail and CPG, and Public Services. Consolidated revenues as of 12 months ending June 2026totaled $14.8billion.