Senior Design Verification Engineer

Mulya Technologies; Bengaluru; On-site; INR 2,500,000 - 4,500,000; Full time

Job summary

Mulya Technologies in Bengaluru seeks an experienced ASIC Verification Engineer to lead verification of complex SoCs. You will design UVM testbenches, run RTL/regression tests and report DV metrics, ensuring high quality, clock-timing, and power management validation.

The role requires strong SystemVerilog/Verilog skills, ARMv8 knowledge, and scripting (Python/Perl). You will collaborate with design teams and customers to deliver robust silicon solutions.

Qualifications

• BS or MS in Computer Science or Electrical Engineering.
• 5–10+ years of industry experience bringing silicon ICs into high volume production.
• Must have strong experience with UVM.
• Must have full chip verification experience.
• Experience leading a single project.
• Knowledge of industry standard interfaces; extensive familiarity with Verilog, simulation tools; ability to debug problems in Real Time.
• Sound knowledge of ARMv8, interconnect, memory coherence and memory architecture.
• Familiarity with Formality and verification tools (DFX, low power).
• Expertise in writing Perl / Python, awk, sed & common scripts to automate verification tasks for CPU and chip peripherals – USB, PCIe, MIPI, SDIO, PCIe & DDR controllers.
• Advanced knowledge of ASIC design and verification flow including RTL design, simulation, test bench development, regression, equivalence checking, timing analysis, scan insertion and test pattern generation.
• Experience with low-level programming of systems in C/C++.
• Functional understanding of constrained random verification, functional coverage, and code coverage; UPF low power verification.
• Team player with excellent communication skills and willingness to tackle diverse challenges.

Responsibilities

• Verify methodology and ensure uniform standards; adopt best practices across projects.
• Collaborate with Design Verification teams at customer sites to identify gaps and implement corrective actions.
• Oversee ASIC verification, implement test benches in UVM/SystemVerilog, run RTL and gate-level regressions, generate DV metrics, and debug issues.
• Lead debugging and troubleshooting in real time for high throughput, low latency pipelines and dynamic power management.
• Set up verification regression suites at RTL and netlist levels after synthesis to cover corner cases.
• Work with design teams to meet requirements; review specifications, understand chip architecture, and define tests and coverage plans.
• Coordinate with Custom SoC teams to provide excellent customer service and timely, accurate deliverables.

Skills

UVM

SystemVerilog

Verilog

RTL debugging

C/C++

Python

Perl

Tcl

Constrained random

Code coverage

Memory architecture

ARMv8

DFx

Education

BS in CS or EE

MS in CS or EE

Tools

Verilog simulators

Emulation tools

FPGA validation

Job description

Top 100 Global Semiconductor MNC in the world

Description

We are a innovative enterprise that designs, develops, and delivers System-on-Chip products to customers worldwide. The company is focused on AR/VR, imaging, networking, storage, and other dynamic technologies that drive today’s leading-edge applications. We combine world-class expertise, experience, and an extensive IP portfolio to provide exceptional solutions and ensure a better quality of experience for customers. Founded in 2015, We are headquartered in Japan, and have offices in Japan, Asia, United States and Europe to lead its product development and sales activities.

Primary Responsibilities Include:

• Responsible for all aspects of verification methodology employed and for ensuring the application of uniform standards and adoption of best practi
• ces.Work and liaison with other Design Verification teams within our customer sites to identify holes in the design verification flow and implement corrective act
• ion.Overall, responsible for verification of ASIC designs To include such things
• as:Design Verification – Implement test benches in UVM and Sytem Verilog, run regressions at RTL and gate level, generate and report DV metrics with respect to bug tracking and code coverage,debug failures and providefeedback to the designt
• eam.Responsible for oversight and completion of debugging problems and troubleshooting in Real Time. This includes being responsible forDebugging Designs for High throughput, Low Latency of Pipeline and DynamicPower Management at full system le
• vel.Setup Verification Regression suites at RTL Level & Corresponding NetlistLevel after Synthesis to test any/all Cornercase conditi
• ons.Work closely with design team to ensure the Company is meeting design requirements for projects. This may include: review of specifications, understanding chip architecture, developing tests & coverage plans, and defining methodology & test benc
• hes.Work closely with Custom SoC department to provide great customer service to our clients and the projects at hand. Support, encourage and drive timelyand accurate deliverables with customers withinsched
• ules

Necessary Qualifications:

• BS or MS in Computer Science or Electrical Engine
• ering.5-10+ years of industry experience bringing silicon ICs into high volume produ
• ction.Must have strong experience wit
• h UVM.Must have a full chip verification expe
• rienceExperience of leading a single pr
• oject.Knowledge of industry standard interfaces. Extensive Familiarity with Verilog, Simulation tools & demonstrated ability to debug Problems & Troubleshoot in Rea
• lTime.Sound knowledge of ARMv8, interconnect, memory coherence and memory archite
• cturesFamiliarity with Formality & most popular Verification Tools. (Key knowledge should include such topics as: IP validation, Gate level verification, FPGA Validation, Emulation, Silicon Validation, Reference Board bring up verification, Silicon Bring up, DFx, Low Power Verific
• ation)Expertise in writing Perl / Python , awk, sed & Common Scripts to automate the Verification Tasks for CPU plus all Chip peripherals – USB, PCIe, MIPI, SDIO, PCI E & DDR Controllers.Advanced knowledge of ASIC design and verification flow including RTL design, simulation, test bench development, regression, equivalence checking, timing analysis, scan insertion and test pattern gene
• ration
• Experience with low-level programming of systems in
• C/C++.Experienced in writing scripts in languages such as Perl, Python, an
• d Tcl.Functional understanding of constrained random verification process, functional coverage, and code coverage.Low power verification UPF
• Team player with excellent communication skills and the desire to take on diverse chall

Other Qualifications:

• Good knowledge of low power camera and imaging systems is a plus
• Experience with formal verification tools is
• Familiarity with ARM architecture
• Familiarity with scripting/programming with Perl/Python, Tcl, C/C++