Technical Architect

HCLTech; Bengaluru; Hybrid; INR 3,500,000 - 7,000,000; Full time

Job summary

HCL Technologies Limited in Bengaluru invites a Technical Architect to lead complex physical design tasks for cutting-edge SoC projects. You will own clock tree synthesis, route optimization, and timing closure across modes, corners, and power-down states.

You will resolve DRC/LVS/ERC signoff issues, apply low-power techniques (UPF/Multi-Vt), and collaborate with RTL and micro-architecture teams to drive fast, reliable silicon delivery.

Qualifications

• Experience in physical design and timing closure.
• Familiarity with clock tree synthesis and post-route optimization.
• Knowledge of DRC, LVS, ERC signoff processes.
• Experience with UPF/Multi-Vt/Multi-voltage for low-power designs.

Responsibilities

• TS (Clock Tree Synthesis) routing and post-route optimization.
• Achieve timing closure across modes and corners.
• Resolve DRC, LVS, ERC and signoff violations.
• Handle low-power design techniques: Multi-Vt, Multi-voltage (UPF).
• Collaborate with RTL & Micro-architecture teams.

Skills

Clock tree synthesis

Timing closure

Low-power techniques

Signoff process

Tools

Primetime

Job description

Career Opportunities: Technical Architect (165182)

Requisition ID165182-Posted11/10/2026

Key Responsibilities

TS (Clock Tree Synthesis)RoutingPost‑route optimizationAchieve timing closure across all modes and cornersResolve DRC, LVS, ERC and signoff violationsHandle low‑power design techniques:Multi‑Vt, Multi‑voltage (UPF)

Skill Requirements

Power gating, clock gatingPerform physical verification and signoff:STA (Primetime)SI / CrosstalkIR drop & EM analysisWork on advanced nodes (7nm, 5nm, 3nm or below)Collaborate with:RTL & Micro‑architecture teams

Other Requirements

DFT & Test engineersFoundry and CAD teamsDebug complex timing, congestion, power, and variability issuesDrive methodology improvements and automation (scripts/flows)