ASIC - Physical Design Engineer

Vicharak; Surat; On-site; INR 4,500,000 - 7,500,000; Full time

Benefits offered by this job

Job summary

Vicharak in Surat, Gujarat—an advanced backend leadership role for RTL-to-GDSII in complex IP/SoC subsystems. You will own end-to-end flow and de-risk the design while building a scalable team.

You will define methodology, drive sign-off, and collaborate with RTL/digital and full-custom layout teams to deliver robust, power-aware implementations across nodes.

Qualifications

• End-to-end RTL-to-GDSII expertise required.
• Hands-on power optimization and glitch reduction experience.
• Strong timing-closure and MCMM STA experience.

Responsibilities

• Define and maintain a modern RTL-to-GDS flow with constraints, libraries/PDKs, UPF/CPF, and sign-off checks.
• Lead synthesis, floorplanning, partitioning, P&R, CTS, routing, extraction, and closure.
• Set predictable PPA targets and lead ECOs; ensure timing and power alignment post-layout.
• Integrate custom macros, SRAMs, and I/O; manage clocking, CDC, and hierarchical/hard-macro integration with LEF.
• Own power intent (UPF/CPF), isolation/retention strategies, and power-aware STA/simulation.
• Partner with DFT on scan/MBIST insertion and test timing; protect test coverage.
• Industrialize the flow with Tcl/Python automation and CI/CD for nightly builds.
• Engage with foundries on PDK updates, antennas, density rules, and reliability guidance.

Skills

RTL to GDSII flow

Synthesis

Floorplanning

P&R

CTS

Timing closure

Power optimization

UPF/CPF

DFA/DFT

Tcl scripting

Python scripting

Version control

Foundry liaison

Multi-voltage design

Hierarchy integration

Clock tree synthesis

Tools

Synopsys

Cadence

LEF/abstracts

Job description

Own the end-to-end RTL-to-GDSII implementation for complex IP/SoC subsystems and build the backend team that scales it. You’ll define the methodology, constraints, and quality metrics that the team shall adhere to. The team you lead will be responsible for synthesis, floor planning, P&R, clock tree synthesis, multi-corner STA, design for testability, and ECOs to achieve sign-off. You and your team will collaborate tightly not only with our RTL/digital team but also with our full-custom and full-custom layout team, integrating our full-custom design blocks into a digital-on-top mixed ASIC design. This is a hands-on technical leadership role, where you will not only set the flow and lead the team, but also personally de-risk and own the most challenging aspects of the design.

What you’ll do

• Methodology: Define and maintain a modern RTL-to-GDS flow, including constraint strategy, libraries/PDKs, UPF/CPF, and sign-off checks.
• Implementation: Run synthesis, floorplan, partitioning, P&R, CTS, routing, extraction, and closure.
• PPA & quality: Create predictable PPA targets and tracking, lead timing/power ECOs; correlate pre/post-layout timing
• Integration: Integrate custom macros, SRAMs, and I/O, manage clocking strategy, CDC, and hierarchical/hard-macro integration with LEF.
• Low power: Own power intent (UPF/CPF), isolation/retention strategies, level shifting, and power-aware STA/simulation.
• DFT & test hooks: Partner with DFT on scan/MBIST insertion and test timing; ensure routes and constraints don’t compromise test coverage or bring-up.
• Automation & CI: Industrialize the flow with Tcl/Python automation, reproducible configurations, metrics dashboards, and CI/CD for nightly builds and regression testing.
• Foundry interface: Engage with foundries on PDK updates, waiver handling, antenna/density rules, and reliability guidance; maintain the flow of information.

Requirements

• Deep expertise in one complete tool chain (Synopsys or Cadence)
• Hands-on experience in power-optimization techniques, including glitch reduction and activity-based power correlation (VCD/SAIF).
• Strong MCMM STA and timing-closure experience
• Experience with grid planning, IR/EM analysis, and fixes. Proven floorplanning/partitioning and hierarchical integration (hard-macros, abstracts/LEF, feedthroughs, blockage strategy).
• UPF/CPF know-how for multi-voltage, power-gated designs, including isolation/retention and power-aware STA and sim.
• Scripting for automation (Tcl, Python) and version control (Git, Perforce, or similar)
• Ability to work and lead the activities independently and assume responsibility for major decisions

Nice to have

• DFT exposure (scan planning, test timing, MBIST integration) and formal equivalence workflows.
• Package/board co-design awareness (bump/rail planning, SSO/PI, thermal assumptions).
• Experience at advanced nodes (≤ 7 nm FinFET) with multi-patterning/EUV constraints and variability considerations.
• Familiarity with sign-off for safety-/quality-critical markets (automotive-style reliability targets, waiver governance, documentation rigor).