Senior Technical Architect

HCLTech; Bengaluru; On-site; INR 3,500,000 - 5,500,000; Full time

Job summary

HCL Technologies Limited, Bengaluru, seeks a Senior Technical Architect to own end-to-end physical design flow, from floorplanning to signoff, across nodes such as 7nm/5nm and below. The role focuses on timing closure, power management, and signoff across multiple corners.

You will collaborate with RTL and micro-architecture teams, DFT & Test, foundry and CAD groups, driving low-power techniques and automation of workflows.

Qualifications

• 15–20 years of experience in physical design and related areas.
• B.Tech / M.Tech in Electrical or Electronics Engineering.

Responsibilities

• End-to-end physical design flow: Floorplanning, Power planning, Placement & optimization, CTS, Routing, Post-route optimization.
• Achieve timing closure across all modes and corners; handle DRC, LVS, ERC and signoff violations.
• Work on advanced nodes (7nm, 5nm or below) and drive methodology improvements and automation (scripts/flows).
• Own full-chip STA signoff for all PVT corners and modes (functional, scan, low-power, etc.).

Education

B.Tech / M.Tech in Electrical or Electronics Engineering

Job description

Career Opportunities: Senior Technical Architect (190007)

Requisition ID190007-Posted11/08/2026

B.Tech / M.Tech in Electrical or Electronics Engineering. Experince 15 to 20 years. Perform end‑to‑end physical design flow:

• Floorplanning
• Power planning (PG grid, IR)
• Placement & optimization
• CTS (Clock Tree Synthesis)
• Routing
• Post‑route optimization
• Achieve timing closure across all modes and corners
• Resolve DRC, LVS, ERC and signoff violations
• Handle low‑power design techniques:

Key Responsibilities

• Multi‑Vt, Multi‑voltage (UPF)
• Power gating, clock gating
• Perform physical verification and signoff:
• STA (Primetime)
• SI / Crosstalk
• IR drop & EM analysis
• Work on advanced nodes (7nm, 5nm, 3nm or below)
• Collaborate with:
• RTL & Micro‑architecture teams
• DFT & Test engineers
• Foundry and CAD teams
• Debug complex timing, congestion, power, and variability issues
• Drive methodology improvements and automation (scripts/flows)
• Own full-chip STA signoff for all PVT corners and modes (functional, scan, low-power, etc.)
• Drive timing closure at chip level, including setup/hold, noise, OCV/AOCV/POCV