Engineer, IPDev Layout

Micron Technology, Inc; Hyderabad; On-site; INR 1,200,000 - 1,800,000; Full time

Job summary

Micron Technology, Inc is seeking an experienced Engineer for their DPG-IPDEV Team in Bangalore, India. The successful candidate will design and develop critical analog and mixed-signal IPs, focusing on high-performance computing solutions.

This role involves collaborating with global engineering teams and requires 5-8 years of relevant experience. The ideal candidate will have proficiency in Cadence tools and a strong understanding of analog layout fundamentals.

Micron is committed to equal employment opportunities for all qualified applicants.

Qualifications

• 5-8 years of analog/custom layout experience.
• Proficiency in Cadence VLE/VXL and Mentor Graphic Calibre DRC/LVS.
• Excellent problem-solving skills in physical verification of custom layout.

Responsibilities

• Design and develop critical analog and mixed-signal custom digital blocks.
• Perform layout verification including LVS/DRC/Antenna checks.
• Deliver block-level layouts on time with acceptable quality.

Skills

Analog layout experience

Proficiency in Cadence VLE/VXL

Hands-on experience with temperature sensor, PLL, ADC, DAC

Understanding of analog layout fundamentals

Problem-solving skills

Excellent verbal and written communication

Proactive exploration of AI tools

Education

BE or MTech in Electronic/VLSI Engineering

Job description

Req. ID: JR97408 – Engineer, IPDev Layout

Location: Bangalore, India

Overview

Micron Technology’s DPG-IPDEV Team develops world‑class analog and mixed‑signal IPs used in every cutting edge DRAM chip. The Layout Design Engineer will work on AI and high‑performance computing solutions such as High Bandwidth Memory and collaborate with global engineering teams across multiple projects.

Role and Responsibilities

• Design and develop critical analog, mixed‑signal, custom digital blocks and provide full‑chip level integration support.
• Perform layout verification including LVS/DRC/Antenna, quality checks, and documentation.
• Deliver block‑level layouts on time with acceptable quality.
• Plan, estimate area/time, schedule, and execute to meet project milestones in a multi‑project environment.
• Contribute to project‑management activities.
• Communicate effectively with global engineering teams to ensure layout project success.
• Explore and leverage AI‑related tools in day‑to‑day tasks.

Qualification / Requirements

• 5–8 years of analog/custom layout experience in advanced CMOS processes across various technology nodes (Planar, FinFET).
• Proficiency in Cadence VLE/VXL and Mentor Graphic Calibre DRC/LVS is required.
• Hands‑on experience creating layouts for critical blocks such as temperature sensor, PLL, ADC, DAC, LDO, bandgap, reference generators, charge pump, current mirrors, comparators, differential amplifiers, etc.
• Strong understanding of analog layout fundamentals (matching, electro‑migration, latch‑up, coupling, crosstalk, IR‑drop, passive device parasitics, etc.).
• Awareness of how layout affects circuit speed, capacitance, power, and area.
• Ability to understand build constraints and implement high‑quality layouts.
• Knowledge of build hierarchy and different architectures for memory designs.
• Excellent problem‑solving skills in physical verification of custom layout.
• Experience with multiple tape‑out support is an advantage.
• Excellent verbal and written communication skills.
• Proactive exploration of AI tools.

Education

BE or MTech in Electronic/VLSI Engineering.

Equal Employment Opportunity

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.

Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.