Layout engineer

Micron Technology, Inc; Hyderabad; On-site; INR 1,200,000 - 2,400,000; Full time

Job summary

Micron Technology, Inc. in Bangalore, India, is seeking a Layout Design Engineer to contribute to analog and mixed-signal IPs used in DRAM devices.

You will collaborate with global teams on multi-project assignments and help ensure high‑quality layouts that meet timing and power goals. The role requires 3–6 years in analog/custom layout, proficiency with Cadence VLE/VXL and Mentor Calibre, and solid understanding of layout fundamentals, LVS/DRC, and tape-out processes.

Qualifications

• 3 to 6 years' experience in analog/custom layout design in advanced CMOS process.
• Expertise in Cadence VLE/VXL and Mentor Graphic Calibre DRC/LVS is a must.
• Experience creating layout of critical blocks such as Temperature sensor, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier.
• Good understanding of Analog Layout fundamentals (matching, EMI, crosstalk, IR-drop, parasitics).
• Understanding layout effects on speed, capacitance, power and area.

Responsibilities

• Design and development of analog, mixed-signal, and full chip layout blocks.
• Perform LVS/DRC/antenna checks and documentation.
• Ensure on-time delivery of block-level layouts with quality.
• Plan and estimate area/time, coordinate across multiple projects.
• Contribute to project management and cross-team communication.
• Present layout status to global engineering teams.

Skills

Analog layout

Cadence VLE/VXL

Mentor Calibre DRC/LVS

Critical block layout

Analog layout fundamentals

Design hierarchy

Memory design architectures

Physical verification

Tape-out support

AI-related tools exploration

Education

BE or MTech in Electronic/VLSI Engineering

Tools

Cadence VLE/VXL

Mentor Calibre DRC/LVS

Job description

Req. ID: JR107636 Layout engineer

Our vision is to transform how the world uses information to enrich life for all.

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

For more than 45 years, Micron Technology, Inc. has redefined innovation with the world’s most advanced memory and semiconductor technologies. We’re an international team of visionaries and scientists, developing groundbreaking technologies that are transforming how the world uses information to enrich life.

We are looking for Layout Design engineer at our Micron Technology’s DPG-IPDEV Team in Bangalore, India. DPG-IPDEV team is responsible for developing world‑class analog and mixed signal IPs used in every groundbreaking DRAM chip produced in Micron. As a Layout Design engineer, you will be working for intensive applications such as artificial intelligence and high‑performance computing solution, High Bandwidth Memory. As a Layout Design Engineer you will be collaborating with peer teams crossing Micron global footprint, in a multiple projects‑based environment.

Role and Responsibilities

• Responsible for Design and development of critical analog, mixed‑signal, custom digital block, and full chip level integration support.
• Perform layout verification like LVS/DRC/Antenna, quality check and support documentation.
• Responsible for on‑time delivery of block‑level layouts with acceptable quality.
• Demonstrate leadership skills in planning, area/time estimation, scheduling, and execution to meet project schedule/milestones in multiple project environment.
• Contribute to effective project‑management.
• Effectively presenting with Global engineering teams to assure the success of layout project.

Qualification/Requirements

• 3 to 6years' experience in analog/custom layout design in advanced CMOS process, in various technology nodes (Planar, FinFET )
• Expertise in Cadence VLE/VXL and Mentor Graphic Calibre DRC/LVS is a must.
• Should have hands on experience in creating layout of critical blocks such as Temperature sensor, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier etc.,
• Good understanding of Analog Layout fundamentals (e.cg., Matching, Electro‑migration, Latch‑up, coupling, crosstalk, IR‑drop, active and passive static device parasitics etc.)
• Understanding layout effects on the circuit such as speed, capacitance, power and area etc.
• Ability to understand design constraints and implement high‑quality layouts
• Ability to understand design hierarchy and different architectures for Memory designs.
• Excellent problem‑solving skills in physical verification of custom layout.
• Multiple Tape out support experience will be an added advantage.
• Excellent verbal and written communication skills.
• Should be proactive in exploring AI‑related tools in day‑to‑day tasks.

Education

BE or MTech in Electronic/VLSI Engineering

Job Profile(s):

Semiconductor Design Engineer 2

Relocation level: (TBD)

Benefits

• Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future.
• We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget.
• Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave.
• Additionally, Micron benefits include a robust paid time‑off program and paid holidays.

All qualified applicants will be considered for employment regardless of race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.

Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.