Layout Engineer, DPG IP DEV Layout

Micron Technology, Inc; Bengaluru; On-site; INR 1,200,000 - 2,200,000; Full time

Benefits offered by this job

Medical, dental and vision plans

Paid time off & holidays

Job summary

Micron Technology, Inc. in Bangalore, India, is seeking a Layout Design Engineer for the DPG-IPDEV team.

You will contribute to the design and development of analog and mixed-signal IPs used in modern DRAM, partnering with global teams across multiple projects and applying Cadence and Mentor tools to achieve robust, on-time layouts. The role requires 3–5 years in analog/custom layout, strong knowledge of LVS/DRC, and hands-on experience with blocks like PLL, ADC, DAC, LDO, and current mirrors.

Qualifications

• 3–5 years of experience in analog/custom layout design in advanced CMOS processes (Planar, FinFET)
• Expertise in LVS/DRC and density/area optimization
• Experience with layout of critical blocks (PLL, ADC, DAC, LDO, Bandgap, etc.)
• Knowledge of analog layout fundamentals and layout effects on speed, capacitance, power, and area
• Strong communication and collaboration across global teams

Responsibilities

• Design and development of analog, mixed-signal, and digital blocks and full-chip integration support
• Perform layout verification (LVS/DRC/Antenna) and documentation
• Ensure on-time delivery of block-level layouts with quality
• Lead planning, estimation, scheduling, and execution across multiple projects
• Collaborate with global engineering teams to ensure project success

Skills

Analog layout

Mixed-signal design

Layout verification

Leadership & planning

Communication

Education

BE or MTech in Electronic/VLSI Engineering

Tools

Cadence VLE/VXL

Mentor Calibre DRC/LVS

Job description

Req. ID: JR108571 Layout Engineer, DPG IP DEV Layout

Our vision is to transform how the world uses information to enrich life for all.

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

Job Description

For more than 45 years, Micron Technology, Inc. has redefined innovation with the world’s most advanced memory and semiconductor technologies. We’re an international team of visionaries and scientists, developing groundbreaking technologies that are transforming how the world uses information to enrich life.

We are looking for Layout Design engineer at our Micron Technology’s DPG-IPDEV Team in Bangalore, India. DPG-IPDEV team is responsible for developing world-class analog and mixed signal IPs used in every modern DRAM chip produced in Micron. As a Layout Design engineer, you will be working for intensive applications such as artificial intelligence and high-performance computing solution, High Bandwidth Memory. As a Layout Design Engineer you will be collaborating with peer teams crossing Micron global footprint, in a multiple projects-based environment.

Role and Responsibilities

• Responsible for Design and development of critical analog, mixed-signal, custom digital block, and full chip level integration support.
• Perform layout verification like LVS/DRC/Antenna, quality check and support documentation.
• Responsible for on-time delivery of block-level layouts with acceptable quality.
• Demonstrate leadership qualities in planning, area/time estimation, scheduling, and execution to meet project schedule/milestones in multiple project environment.
• Contribute to effective project-management.
• Effectively communicating with Global engineering teams to assure the success of layout project.

Qualification/Requirements

• 3 to 5 years' experience in analog/custom layout design in advanced CMOS process, in various technology nodes (Planar, FinFET )
• Expertise in Cadence VLE/VXL and Mentor Graphic Calibre DRC/LVS is a must.
• Should have hands on experience in creating layout of critical blocks such as Temperature sensor, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier etc.,
• Good understanding of Analog Layout fundamentals (e.cg., Matching, Electro-migration, Latch-up, coupling, crosstalk, IR-drop, active and passive static device parasitics etc.)
• Understanding layout effects on the circuit such as speed, capacitance, power and area etc.
• Ability to understand design constraints and implement high-quality layouts
• Ability to understand design hierarchy and different architectures for Memory designs.
• Excellent problem-solving skills in physical verification of custom layout.
• Multiple Tape out support experience will be an added advantage.
• Excellent verbal and written communication skills.
• Should be proactive in exploring AI-related tools in day-to-day tasks.

Education

BE or MTech in Electronic/VLSI Engineering

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.

Job Profile(s)

Semiconductor Design Engineer 2

Relocation level: (TBD)

As a world leader in the semiconductor industry, Micron is dedicated to your personal wellbeing and professional growth. Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future. We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget. Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave. Additionally, Micron benefits include a robust paid time-off program and paid holidays. For additional information regarding the Benefit programs available, please see the Benefits Guide posted on Benefits | Micron Technology, Inc

Micron is proud to be an equal opportunity workplace and is an affirmative action employer.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.