STA/Synthesis Engineer

7Rays Semiconductors; Bengaluru; On-site; INR 1,500,000 - 2,500,000; Full time

Job summary

7Rays Semiconductors is seeking a hands-on Timing Closure Lead to drive Synthesis and Static Timing Analysis for complex SoC projects. You will guide a 4–5 member team, coordinate RTL, PD, and HMs teams, and own prelayout and postlayout timing analyses across corners and modes.

The role requires expertise in Synthesis, STA, UPF/DFT SD, and TCL scripting in a UNIX environment, with a focus on achieving robust timing closure and ECO execution.

Qualifications

• Hands-on experience with Synthesis and Static Timing Analysis.
• Experience with UPF cleanup and LEC-based timing signoff.
• Knowledge of DFT SDC, GCA, and timing signoff processes.
• Experience leading a small team and mentoring engineers.

Responsibilities

• Lead STA/Synthesis activities across RTL, PD, and SoC teams.
• Manage timing closure at sub-system, block, and chip levels.
• Develop and fix ECOs to fix timing violations and DRCs.
• Prepare prelayout timing analysis and postlayout timing reports.

Skills

Synthesis

Static Timing Analysis

Timing closure

Logical equivalence check

DFT SDC

UPF cleanup

TCL scripting

UNIX

RTL design

Team leadership

Tools

LEC environment

UPF

VCLP Signoff

Job description

• Hand-on Experience and Comprehensive knowledge of Synthesis and Static Timing Analysis.
• Synthesis Quality with FE Inputs, LEC environment, UPF Cleanup, Generic Partition level UPF ? and VCLP Signoff.
• USER mode SDC (will have generic dft constraints), Generic DFT SDC, GCA, Flat Timing convergence, Timing Signoff, Merging Modes
• Hands-on experience on Logical aware Synthesis, Logical Equivalence check and Static Timing analysis.
• Knowledge on the Timing closure on Sub system level & Block level and Chip level.
• Knowledge on Writing Manual ECO’s to fix timing violations and DRC’s.
• Good Knowledge of TCL scripting and UNIX env.
• Leading the team 4 to 5 team members by guiding and mentoring on the STA /Synthesis.
• Prelayout timing analysis and report out Post layout timing analysis for placement, CTS & PRO Clock gating checks and timing closure ECOs and final tapaout timing closure skills across corners and modes Must work RTL design team, PD team and HMs team for overall timing closure for SoC