Synthesis and backend integration engineer

MediaTek; Bengaluru; On-site; INR 1,200,000 - 2,000,000; Full time

Job summary

MediaTek is looking for a professional with 6-12 years of experience in physical design and synthesis. Candidates should be proficient in PPA optimizations, timing closure, and industry-standard tools such as Fusion Compiler and Innovus. Familiarity with scripting languages like TCL, Perl, or Python is essential. The role involves co-working with multiple engineering teams to achieve PPA targets and requires strong communication and problem-solving skills. A relevant degree (MTech or BTech) is necessary.

Qualifications

• 6-12 years of experience in Top/Block level synthesis.
• Proficient in timing closure (STA) and physical design.
• Ability to work in diverse and remote teams.

Responsibilities

• Co-work with RTL, DFT, and PD engineers to meet PPA targets.
• Drive new tool evaluation and methodology refinement.
• Interact with stakeholders for status reporting and issue resolution.

Skills

Physical Synthesis Flow

PPA Optimizations

Timing and Low Power Design

Equivalence Checks

Low Power Checks

TCL/Perl/Python Scripting

Debugging Skills

Education

MTech or BTech in relevant field

Tools

Fusion Compiler

Genus

Conformal LEC

Formality

Innovus

Primetime

Job description

• Working experience on 7nm and below Technologies.
• Proficient in Physical Synthesis flow and PPA optimizations with emphasis on Timing and Low Power design.
• Proficient in Equivalence Checks, Low power Checks.
• Hands on experience in timing/SDC constraints generation and management and timing report analysis.
• Co-work with RTL, DFT and PD engineers to meet PPA targets.
• Hands on experience with Industry Standard tools Fusion Compiler, Genus, Conformal LEC, Formality, Innovus, Primetime etc.
• Hands on experience with functional ECO flow and implementation.
• Good understanding of UPF.
• Familiar with DFT Architecture.
• Driving new tool evaluation, methodology refinement for PPA optimization for complex subsystem.
• Proficient in scripting languages TCL/Perl/Python script.
• Able to work in a diverse team environment and with remote teams.
• Should be sincere, dedicated, and willing to take up new challenges.
• Self-starter and highly motivated.
• Strong debugging, initiative and analysis/problem solving and presentations skills.
• Interaction with all stake holders which includes weekly/daily status reporting, issue capture and resolution.
• 6-12 years with MTech or BTech with Top/Block level synthesis, Timing closure (STA), Physical Design or related work experience.