STA (Static Timing Analysis) and Synthesis Engineer

7Rays Semiconductors; Bengaluru; On-site; INR 1,800,000 - 2,600,000; Full time

Job summary

7Rays Semiconductors in Bengaluru and Noida is seeking a STA/Synthesis Engineer with 6+ years of experience to drive timing closure for SoC projects, including STA, synthesis, and DFT-ready constraints.

You will collaborate with RTL, PD, and verification teams, lead a 4–5 member STA/Synthesis group, and own prelayout and postlayout timing analyses, ensuring robust signoff across corners.

Qualifications

• 6+ years experience in STA/Synthesis.
• Hands-on synthesis with FE inputs and timing signoff.

Responsibilities

• Lead STA/Synthesis activities for SoC timing closure and BCE constraints.
• Mentor & guide 4–5 member STA/Synthesis team across RTL/PD groups.

Skills

STA/Synthesis

Static Timing Analysis

Team leadership

Scripting (TCL)

Timing closure

Tools

TCL Scripting

UNIX

Job description

At 7Rays Semiconductors (https://7rayssemi.com/), we provide end-to-end VLSI design solutions to help our clients achieve execution excellence. Our team of experts specializes in architecture, RTL design, verification, validation, physical design, implementation, and post-silicon validation using the latest technologies and methodologies

We work closely with our clients, building effective partnerships to deliver high-quality solutions tailored to their needs. With a proven track record of successful projects, we are committed to excellence and innovation in semiconductor design.

Job: STA/Synthesis Engineer

Location- Bangalore and Noida

• 6+ years experience in STA/Synthesis
• Hand-on Experience and Comprehensive knowledge of Synthesis and Static Timing Analysis.
• Synthesis Quality with FE Inputs, LEC environment, UPF Cleanup, Generic Partition level UPF ? and VCLP Signoff.
• USER mode SDC (will have generic dft constraints), Generic DFT SDC, GCA, Flat Timing convergence, Timing Signoff, Merging Modes
• Hands-on experience on Logical aware Synthesis, Logical Equivalence check and Static Timing analysis.
• Knowledge on the Timing closure on Sub system level & Block level and Chip level.
• Knowledge on Writing Manual ECO’s to fix timing violations and DRC’s.
• Good Knowledge of TCL scripting and UNIX env.
• Leading the team 4 to 5 team members by guiding and mentoring on the STA /Synthesis.
• Prelayout timing analysis and report out Post layout timing analysis for placement, CTS & PRO Clock gating checks and timing closure ECOs and final tapaout timing closure skills across corners and modes.
• Must have worked with RTL design team, PD team and HMs team for overall timing closure for SoC.