STA Engineer

HrdWyr; Bengaluru Urban; On-site; INR 1,500,000 - 2,700,000; Full time

Job summary

HrdWyr is seeking an experienced engineer to drive chip-level STA convergence from early stages through signoff in a complex SOC environment. You will participate in floor planning and clock planning at the top level, and define timing constraints for all modes including DFT.

The role involves multimode-multi corner timing analysis, and block/SoC level convergence, synthesis, and equivalence checks. Strong timing concepts and scripting skills are essential.

Qualifications

• 5–8 years of SOC level timing convergence experience.
• Synthesis and equivalence check experience.
• Strong timing concepts.
• Experience with low power design across multiple power domains.
• Automation scripting using TCL/Perl/Python.
• Familiarity with industry EDA tools Tempus and PrimeTime.

Responsibilities

• Responsible for chip level STA convergence from early stages to signoff.
• Participate in top level floor plan and clock planning.
• IP & SoC timing constraints definition for all modes including DFT
• Multimode-multi corner timing analysis.
• Block and SoC level timing convergence.
• Block and SoC level Synthesis.
• Block and SoC level equivalence check.

Skills

SOC timing convergence

Synthesis & EC

Timing concepts

Low power design

Scripting: TCL/Perl/Python

ED A tools Tempus/PrimeTime

Asynchronous clocks exposure

Tools

Tempus

PrimeTime

Job description

• Responsible for chip level STA convergence from early stages to signoff.
• Participate in top level floor plan and clock planning.
• IP & SoC timing constraints definition for all modes including DFT
• Multimode-multi corner timing analysis.
• Block and SoC level timing convergence.
• Block and SoC level Synthesis.
• Block and SoC level equivalence check.

Experience Required:

• 5 to 8 years of experience in SOC level timing convergence
• Synthesis and equivalence check
• Strong timing concepts
• Working knowledge of low power design involving multiple power domains.
• Proficiency in scripting languages such as TCL, Perl, or Python for automation.
• Familiarity with industry-standard EDA tools for STA like Tempus and PrimeTime
• Exposure to complex design having multiple asynchronous clocks.