Hardware Design Engineer 2314

Sunrise Biztech Systems; New Delhi; On-site; INR 1,200,000 - 1,800,000; Full time

Job summary

Sunrise Biztech Systems Pvt. Ltd. in New Delhi seeks a Hardware Design Engineer 3 with 6–9 years of experience. The role focuses on DFT, ATPG, SSN methodology, and scan structures, with hands-on work on RTL, timing and non-timing simulations, and DC/FC tooling.

You will perform DFT DRC checks at RTL, analyze violations, and contribute to scan insertion and verification using Design Compiler or Fusion Compiler, with strong TCL/scripting skills.

Qualifications

• 6–9 years of relevant experience in hardware design and DFT.
• Strong knowledge of DFT/ATPG, scan architecture, and SSN methodology.
• Experience with RTL timing and non-timing simulations and debugging.
• Familiarity with DC/Fusion Compiler and TCL scripting for automation.

Responsibilities

• Strong understanding of Siemens Tessent ATPG tools and SSN methodology.
• Hands-on experience in ICL, PDL, Stuck-at and Transition fault pattern generation.
• Good understanding of scan coverage and coverage analysis.
• Experience with timing and non-timing gate-level simulations and debugging simulation failures.
• Experience performing DFT DRC checks at RTL and analyzing violations.
• Strong knowledge of Scan structures, IEEE 1149.1, IEEE 1687, ATPG methodology and DFT flow.
• Good understanding of timing constraints, synthesis flow and scan insertion using DC/FC.
• Strong TCL/Scripting skills.

Skills

ATPG & DFT

Scan structures

RTL timing sims

DC/FC synthesis

TCL scripting

DFT DRC checks

IEEE standards

Job description

Urgent Hiring!!!

Greetings from Sunrise Biztech Systems Pvt. Ltd.

We are hiring for one of our reputed clients for the following position. If you're interested and your experience matches the requirement, we'd love to hear from you.

Position:Hardware Design Engineer 3

Experience: 6-9 Years

Location: New delhi

Contract:12 Months

Role & responsibilities

• Strong understanding of Siemens Tessent ATPG tools and SSN methodology.
• Hands-on experience in ICL, PDL, Stuck-at and Transition fault pattern generation.
• Good understanding of scan coverage and experience in coverage analysis.
• Experience with timing and non-timing gate-level simulations and debugging simulation failures.
• Experience performing DFT DRC checks at RTL and analyzing violations.
• Strong knowledge of Scan structures, IEEE 1149.1, IEEE 1687, ATPG methodology and DFT flow.
• Good understanding of timing constraints, synthesis flow and scan insertion using Design Compiler (DC) / Fusion Compiler (FC).
• Strong TCL/Scripting skills.