STA Engineer

HCLTech; Pune District; On-site; INR 2,000,000 - 3,200,000; Full time

Job summary

HCLTech in Pune, India seeks a senior engineer to lead clocking strategies, manage timing constraints, and drive STA, CTS, and CDC across the design flow. You will collaborate with design and layout teams, mentor junior engineers, and evaluate new tools and methodologies to improve timing closure.

The role emphasizes adherence to industry best practices and thorough documentation of clocking standards. Excellent communication and deep knowledge of timing analysis are essential to deliver robust,

Responsibilities

• Lead the development and implementation of comprehensive clocking strategies for high-performance ICs.
• Define and manage timing constraints throughout the design flow, ensuring accurate and consistent timing analysis.
• Stay up-to-date with the Perform advanced Static Timing Analysis (STA) using industry-standard tools, identifying potential timing violations and bottlenecks.
• Develop and maintain robust clock tree synthesis (CTS) methodologies for optimal clock distribution and skew control.
• Drive the creation and execution of a comprehensive clock domain crossing (CDC) verification plan.
• Collaborate with design engineers, layout engineers, and other physical design teams to address timing closure challenges.
• Mentor and coach junior engineers, fostering their growth and expertise in clocking, constraints, and STA.
• latest advancements in clocking methodologies, timing analysis tools, and industry best practices.
• Lead the evaluation and implementation of new tools and methodologies for improved timing closure efficiency.
• Develop and maintain comprehensive documentation for clocking, constraints, and STA practices within the team.

Job description

• Lead the development and implementation of comprehensive clocking strategies for high-performance ICs.
• Define and manage timing constraints throughout the design flow, ensuring accurate and consistent timing analysis.
• Stay up-to-date with the Perform advanced Static Timing Analysis (STA) using industry-standard tools, identifying potential timing violations and bottlenecks.
• Develop and maintain robust clock tree synthesis (CTS) methodologies for optimal clock distribution and skew control.
• Drive the creation and execution of a comprehensive clock domain crossing (CDC) verification plan.
• Collaborate with design engineers, layout engineers, and other physical design teams to address timing closure challenges.
• Mentor and coach junior engineers, fostering their growth and expertise in clocking, constraints, and STA.
• latest advancements in clocking methodologies, timing analysis tools, and industry best practices.
• Lead the evaluation and implementation of new tools and methodologies for improved timing closure efficiency.
• Develop and maintain comprehensive documentation for clocking, constraints, and STA practices within the team.