STA Lead Engineer

Mulya Technologies; Bengaluru; On-site; INR 1,200,000 - 1,800,000; Full time

Job summary

Mulya Technologies in India seeks a Lead STA Engineer (11+ years) to ensure timing closure for complex SoC designs. You will analyze, validate, and optimize timing across hierarchies and technology nodes to meet performance, power, and reliability targets.

Responsibilities include performing STA at block and full-chip levels, creating SDC constraints, driving timing closure with PD teams, and building automation scripts (Tcl, Python, Perl) to streamline flows while collaborating with

Qualifications

• Minimum 11+ years of experience in STA/SoC timing of complex designs.
• Experience across block and full-chip levels with multiple corners and modes.
• Strong scripting ability (Tcl, Python, Perl) to automate STA flows.

Responsibilities

• Perform STA at block and full-chip levels across corners, modes, and conditions.
• Create and validate SDC constraints for hierarchical SoCs, including clocking and multi-corner scenarios.
• Drive timing closure during synthesis, place-and-route, and sign-off with optimization collaboration.
• Collaborate with RTL, DFT, synthesis, verification, and physical design teams to resolve timing issues.
• Develop scripts to automate STA workflows, reporting, and constraint validation.

Skills

STA timing

Timing closure

Tcl/Python scripting

Digital design basics

Tools

PrimeTime

Tempus

Job description

Among. The top 4 IT companies, in India ranked by market capitalization and revenue

Role Overview

As a Lead STA Engineer(preferably 11+Yrs Experience ), you will be responsible for ensuring timing closure and sign-off for complex System-on-Chip/Subsystem designs. This involves analyzing, validating, and optimizing timing across multiple design hierarchies and technology nodes to meet performance, power, and reliability targets.

Key Responsibilities

Static Timing Analysis (STA):

Perform STA at block and full-chip levels across multiple corners, modes, and conditions using industry-standard tools (e.g., Synopsys PrimeTime, Cadence Tempus).

Timing Constraints Development:

Create and validate SDC constraints for hierarchical SoC designs, including clocking, multi-mode, and multi-corner scenarios.

Timing Closure:

Drive timing closure during synthesis, place-and-route, and sign-off stages. Generate timing ECOs and collaborate with physical design teams for optimization.

Cross-Functional Collaboration:

Work closely with RTL, DFT, synthesis, verification, and physical design teams to resolve timing issues and ensure design quality.

Automation & Scripting:

Develop scripts (Tcl, Python, Perl) to automate STA flows, reporting, and constraint validation.

Advanced Analysis:

Handle OCV (On-Chip Variation), noise, crosstalk, and derate methodologies for accurate timing sign-off.

Documentation & Reviews:

Maintain STA methodology documents and participate in design reviews.

Guide junior engineers on STA techniques and best practices.

Required Skills & Tools

Strong understanding of digital design principles, clocking, and timing concepts.