Lead STA Engineer

LeadSOC Technologies Pvt Ltd; Bengaluru; On-site; INR 2,500,000 - 4,500,000; Full time

Job summary

LeadSOC Technologies Pvt Ltd in Bengaluru is seeking a Lead STA Engineer to drive static timing analysis for complex ASIC/SoC designs. You will own full-chip STA, perform setup/hold analysis, and push timing closure across multiple modes and corners.

Candidates should have 6–12 years of hands-on STA experience, strong scripting skills (Tcl/Python/Perl), and expertise with PrimeTime. The role demands collaboration with RTL, Synthesis, and Physical Design teams to achieve robust timing and PPA

Qualifications

• 6–12 years of hands-on STA experience.
• Proficient with Synopsys PrimeTime or equivalent.
• Strong knowledge of SDC, MMMC, clocking and timing exceptions.
• Experience with full-chip STA and timing sign-off.

Responsibilities

• Own full-chip/block-level STA across modes and corners.
• Perform setup/hold analysis, timing closure and ECO implementation.
• Develop and validate SDC constraints, clock definitions and timing exceptions.
• Analyze MMMC, OCV/AOCV/POCV, SI and clock-related timing issues.
• Drive timing correlation across Synthesis, P&R and sign-off.
• Debug and resolve setup, hold, max transition, max capacitance and constraint violations.
• Work with RTL, Synthesis, Physical Design and DFT for timing closure.
• Drive PPA and timing optimization for high-performance SoCs.
• Develop/debug STA flows and automation using Tcl/Python/Perl.
• Support sign-off, tape-out and critical timing closure activities.

Skills

STA fundamentals

Timing analysis

Full-chip STA

Clocking analysis

OCV/AOCV/POCV

SI timing

Tools

Synopsys PrimeTime

Tcl

Python

Perl

Job description

We are looking for a Lead STA Engineer with strong hands‑on expertise in Static Timing Analysis and timing closure for complex ASIC/SoC designs.

Key Responsibilities

• Own full‑chip/block‑level STA across multiple modes and corners.
• Perform setup/hold analysis, timing closure and ECO implementation.
• Develop and validate SDC constraints, clock definitions and timing exceptions.
• Analyze MMMC, OCV/AOCV/POCV, SI and clock‑related timing issues.
• Drive timing correlation across Synthesis, P&R and sign‑off.
• Debug and resolve setup, hold, max transition, max capacitance and constraint violations.
• Work closely with RTL, Synthesis, Physical Design and DFT teams for timing closure.
• Drive PPA and timing optimization for high‑performance SoCs.
• Develop/debug STA flows and automation using Tcl/Python/Perl.
• Support sign‑off, tape‑out and critical timing closure activities.

Required Skills

• 6–12 years of relevant STA experience.
• Strong hands‑on expertise in Synopsys PrimeTime or equivalent STA tools.
• Strong understanding of SDC, MMMC, clocking, timing exceptions and STA fundamentals.
• Experience with OCV/AOCV/POCV, SI and advanced‑node designs.
• Good understanding of ASIC implementation and physical design flow.
• Strong scripting skills in Tcl/Python/Perl.
• Experience in full‑chip STA and timing sign‑off preferred.